print for mem transaction

5 files changed, 33 insertions, 3 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 83e76fe..72ece0b 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -352,6 +352,7 @@ void warp_inst_t::generate_mem_accesses()
         ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size );
     }
     m_mem_accesses_created=true;
+    print_m_accessq();
 }
 
 void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type )
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 9c418fa..d628745 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -933,7 +933,18 @@ public:
         for(unsigned i=0; i<num_addrs; i++)
             m_per_scalar_thread[n].memreqaddr[i] = addr[i];
     }
-
+    void print_m_accessq(){
+    		
+		if(accessq_empty())
+			return;
+		else{
+			printf("Printing mem access generated\n");
+			std::list<mem_access_t>::iterator it;	
+			for (it = m_accessq.begin(); it != m_accessq.end(); ++it){
+   				 printf("MEM_TXN_GEN:%s:%x, Size:%d \n",mem_access_type_str(it->get_type()), it->get_addr(),it->get_size());
+			}	
+		}
+    }   
     struct transaction_info {
         std::bitset<4> chunks; // bitmask: 32-byte chunks accessed
         mem_access_byte_mask_t bytes;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 42c63ca..52d89f2 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -3354,31 +3354,41 @@ void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t &inst)
 		printf("vp_ld: thrx=%d,addr=%x, base_addr=%x, size=%d, stride=%d\n",thrd,new_addr,addr,size,src2_data.u32);
 
 	if(wmma_type==LOAD_A||wmma_type==LOAD_C){
+			printf("lda/c:");
 		for(i=0;i<8;i++){
 			if(wmma_layout==ROW){
 				//mem->read(new_addr+4*i,size/8,&data[i].s64);
 				mem->read(new_addr+4*i,size/8,&data[i].s64);
+				printf("%x ", new_addr+4*i);
 				mem_txn_addr[num_mem_txn++]=new_addr+4*i;			
 			}
 			else if(wmma_layout==COL){
 				//mem->read(new_addr+4*stride*i,size/8,&data[i].s64);
+				printf("%x ", new_addr+4*stride*i);
 				mem->read(new_addr+4*stride*i,size/8,&data[i].s64);
 				mem_txn_addr[num_mem_txn++]=new_addr+4*stride*i;			
 			}
 		}
+	
 	}
+	
 	else if(wmma_type==LOAD_B4){
+			printf("ldb4:");
 			if(wmma_layout==ROW){
 				mem->read(new_addr,size/8,&data[0].s64);
+				printf("%x ",new_addr);
 				mem_txn_addr[num_mem_txn++]=new_addr;			
 			}
 			else if(wmma_layout==COL){
 			}
 	}
 	else if(wmma_type==LOAD_B8){
+			printf("ldb8:");
 			if(wmma_layout==ROW){
 				mem->read(new_addr,size/8,&data[0].s64);
 				mem->read(new_addr+4,size/8,&data[1].s64);
+				printf("%x ",new_addr,new_addr+4);
+			
 				mem_txn_addr[num_mem_txn++]=new_addr;			
 				mem_txn_addr[num_mem_txn++]=new_addr+4;			
 			}
@@ -3387,12 +3397,13 @@ void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t &inst)
 			}
 	}
 	else if(wmma_type==LOAD_B16){
-			printf("LOADB16_MODE");
+			printf("ldb16:");
 			if(wmma_layout==ROW){
 				mem->read(new_addr,size/8,&data[0].s64);
 				mem->read(new_addr+4,size/8,&data[1].s64);
 				mem->read(new_addr+8,size/8,&data[2].s64);
 				mem->read(new_addr+12,size/8,&data[3].s64);
+				printf("%x ",new_addr,new_addr+4,new_addr+8,new_addr+12);
 				mem_txn_addr[num_mem_txn++]=new_addr;			
 				mem_txn_addr[num_mem_txn++]=new_addr+4;			
 				mem_txn_addr[num_mem_txn++]=new_addr+8;			
@@ -3405,6 +3416,8 @@ void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t &inst)
 		printf("wrong vp_load type\n");;
 		abort();
 	}
+	printf("\n");
+
 	//generate timing memory request
    	inst.space = space;
    	inst.set_addr(thrd, (new_addr_type *)mem_txn_addr , num_mem_txn);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 5e80fb1..e745f03 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -741,7 +741,10 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst )
 {
     execute_warp_inst_t(inst);
     if( inst.is_load() || inst.is_store() )
-        inst.generate_mem_accesses();
+    {
+	inst.generate_mem_accesses();
+        //inst.print_m_accessq();	
+    }	
 }
 
 void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id )
@@ -1512,6 +1515,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        // bypass L1 cache
        unsigned control_size = inst.is_store() ? WRITE_PACKET_SIZE : READ_PACKET_SIZE;
        unsigned size = access.get_size() + control_size;
+       //printf("Interconnect:Addr: %x, size=%d\n",access.get_addr(),size);
        if( m_icnt->full(size, inst.is_store() || inst.isatomic()) ) {
            stall_cond = ICNT_RC_FAIL;
        } else {
diff --git a/src/gpgpu-sim/traffic_breakdown.cc b/src/gpgpu-sim/traffic_breakdown.cc
index 32f0d30..587067f 100644
--- a/src/gpgpu-sim/traffic_breakdown.cc
+++ b/src/gpgpu-sim/traffic_breakdown.cc
@@ -46,6 +46,7 @@ std::string traffic_breakdown::classify_memfetch(class mem_fetch * mf)
       break; 
    default: assert(0 && "Unknown traffic type"); 
    }
+   printf("%s:Icnt:%s:Request: %x,Size%d,DataSize:%d,CntrlSize%d:\n",m_network_name.c_str(),traffic_name.c_str(),mf->get_addr(),mf->size(),mf->get_data_size(),mf->get_ctrl_size());
    return traffic_name; 
 }