diff options
| author | Dongdong Li <[email protected]> | 2013-10-09 02:56:03 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:50:59 -0700 |
| commit | 3c71147d4138fbed4334a70c80b70a54539cce35 (patch) | |
| tree | ba72d6e4c3dff94c9b8e372dd028eab4554e1d7a | |
| parent | 62e9f666a8c69e9820096860cf3e1d64a709baea (diff) | |
Bug FIX: icnt::full() check using wrong mf size
Review ID: 89001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
| -rw-r--r-- | CHANGES | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.cc | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 3 | ||||
| -rw-r--r-- | src/intersim2/interconnect_interface.cpp | 3 |
4 files changed, 7 insertions, 2 deletions
@@ -55,6 +55,7 @@ Version 3.2.1+edits (development branch) versus 3.2.1 BookSim 2.0. - Added the ability to trace all the shader cores in the SHADER_DPRINTF - Bug Fixes: + - Fixed icnt::full() check using wrong mf size - Fixed the flit count sent to GPUWattch for atomic operations. - Fix for Bug 51 - Updated the function declaration of clCreateContextFromType(). diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 469d6dd..2137d2e 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -635,7 +635,7 @@ bool baseline_cache::bandwidth_management::fill_port_free() const void baseline_cache::cycle(){ if ( !m_miss_queue.empty() ) { mem_fetch *mf = m_miss_queue.front(); - if ( !m_memport->full(mf->get_data_size(),mf->get_is_write()) ) { + if ( !m_memport->full(mf->size(),mf->get_is_write()) ) { m_miss_queue.pop_front(); m_memport->push(mf); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 230af89..fbf9d52 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1379,7 +1379,6 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea assert( !inst.accessq_empty() ); mem_stage_stall_type stall_cond = NO_RC_FAIL; const mem_access_t &access = inst.accessq_back(); - unsigned size = access.get_size(); bool bypassL1D = false; if ( CACHE_GLOBAL == inst.cache_op || (m_L1D == NULL) ) { @@ -1392,6 +1391,8 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea if( bypassL1D ) { // bypass L1 cache + unsigned control_size = inst.is_store() ? WRITE_PACKET_SIZE : READ_PACKET_SIZE; + unsigned size = access.get_size() + control_size; if( m_icnt->full(size, inst.is_store() || inst.isatomic()) ) { stall_cond = ICNT_RC_FAIL; } else { diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index eecf96e..81f6c82 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -143,6 +143,9 @@ void InterconnectInterface::Init() void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_deviceID, void *data, unsigned int size) { + // it should have free buffer + assert(HasBuffer(input_deviceID, size)); + int output_icntID = _node_map[output_deviceID]; int input_icntID = _node_map[input_deviceID]; |