diff options
| author | Tim Rogers <[email protected]> | 2019-05-02 16:11:34 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-05-02 16:11:34 -0400 |
| commit | 4697483b3fffcdfcf81a4199d87c1255a8b55729 (patch) | |
| tree | 3e422d596167ebde1a0fdf9994bee87d66843426 | |
| parent | bbef52a122761bc8f02092e0acf867dbd87cbe70 (diff) | |
| parent | f507979bcf0f14d1e5843c9b08613d6b0a4bb7a2 (diff) | |
Merge branch 'dev' into dev
| -rw-r--r-- | aerialvision/organizedata.py | 2 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.h | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py index 0d6cd91..090b90f 100644 --- a/aerialvision/organizedata.py +++ b/aerialvision/organizedata.py @@ -97,7 +97,7 @@ def organizedata(fileVars): 'sparse':OrganizeSparse, # Vector data with 2D index (used by DRAM access stats) 'custom':0 } - data_type_char = {int:'I', float:'f'} + data_type_char = {int:'I', float:'f'} print "Organizing data into internal format..." diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 13d8c8f..ae35fef 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -86,7 +86,7 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adpative_volta_cache_config 1 +-adaptive_volta_cache_config 1 # Volta unified cache has four ports -mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3f1fc7e..988ecd1 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -317,8 +317,8 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config, - "adpative_volta_cache_config", + option_parser_register(opp, "-adaptive_volta_cache_config", OPT_BOOL, &adaptive_volta_cache_config, + "adaptive_volta_cache_config", "0"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 09be1f6..2dadd72 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2966,7 +2966,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const abort(); } - if(adpative_volta_cache_config && !k.volta_cache_config_set) { + if(adaptive_volta_cache_config && !k.volta_cache_config_set) { //For Volta, we assign the remaining shared memory to L1 cache //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x unsigned total_shmed = kernel_info->smem * result; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 2204697..86c582f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1518,8 +1518,8 @@ struct shader_core_config : public core_config //Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; - bool adpative_volta_cache_config; bool fast_execution_mode; + bool adaptive_volta_cache_config; }; struct shader_core_stats_pod { |