Fixing a bug that was trashing the LD_LIBRARY_PATH if GPGPUSIM_ROOT was not the first entry in the list

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15422]

2 files changed, 64 insertions, 45 deletions

diff --git a/CHANGES b/CHANGES
index 8fb6d6a..1c4aaff 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,15 +1,22 @@
 LOG:
 Version 3.2.0+edits (development branch) versus 3.2.0
 - Added kernel name and launch uids to performance statistics log.
-- Added l2_cache_config class to extend baseline cache_config. Allows for custom,
-  L2 cache specific functions (such as tag/set index generation functions).  
-- For clarity, renaming '-gpgpu_dram_sched_queue_size' to '-gpgpu_frfcfs_dram_sched_queue_size'.
-- Print the max and the average queue size statistics for FRFCFS scheduling only.
-- New gpgpu_dram_return_queue_size option, which specifies the size of the return queue from the DRAM. 
-- Added a dynamic_warp_id field to each shdr_warp_t. dynamic_warp_id differs from warp_id in that different warps
-  using the same warp scheduling slot (because one warp has finished and another has taken it's place)
+- Added l2_cache_config class to extend baseline cache_config. Allows for
+  custom, L2 cache specific functions (such as tag/set index
+  generation functions).  
+- For clarity, renaming '-gpgpu_dram_sched_queue_size' to
+  '-gpgpu_frfcfs_dram_sched_queue_size'.
+- Print the max and the average queue size statistics for FRFCFS scheduling
+  only.
+- New gpgpu_dram_return_queue_size option, which specifies the size of
+  the return queue from the DRAM. 
+- Added a dynamic_warp_id field to each shdr_warp_t. dynamic_warp_id differs
+  from warp_id in that different warps
+  using the same warp scheduling slot (because one warp has finished and
+  another has taken it's place)
   have the same warp_id but different dynamic_warp_ids.
-- Added extensions to the cache class hierarchy to allow for the use of custom tag_array objects.
+- Added extensions to the cache class hierarchy to allow for the use of custom
+  tag_array objects.
 - Added some additional const-correctness
 - Added a check in cache_config to prevent configuration that specifies a
   writeback cache with allocation-on-fill policy.  The current implementation
@@ -17,20 +24,25 @@ Version 3.2.0+edits (development branch) versus 3.2.0
   generates any writeback traffic.  Even if the writeback traffic is generated,
   the configuration (writeback cache + allocation-on-fill) will inevitably lead
   to deadlock.  
-- Added the ability plot stats with an increasing number of data points in aerielvision.
-  Developers can now add statistics for plotting where the number of entries in each slice is not known
-  initially.
-- Added aerialvision support for profiling which warps issue on a sampling shader.
-  This is a cycle by cycle breakdown of what warpi_ids/dynamic_warp_ids the shader issued
-  on a given core over time plotted as a stacked bar chart.
-  For example, by default every 500 cycles you get a colored breakdown of what warps issued during those cycles.
-- Added DPRINTF support to gpgpusim. Allows for dynamically enabled print streams.
-  Currently the warp scheduler and scoreboard use this system. All prints done after reading the
-  configuration file should be moved to use it.
+- Added the ability plot stats with an increasing number of data points in
+  aerielvision. Developers can now add statistics for plotting where the number
+  of entries in each slice is not known initially.
+- Added aerialvision support for profiling which warps issue on a sampling
+  shader.
+  This is a cycle by cycle breakdown of what warpi_ids/dynamic_warp_ids the
+  shader issued on a given core over time plotted as a stacked bar chart.
+  For example, by default every 500 cycles you get a colored breakdown of what
+  warps issued during those cycles.
+- Added DPRINTF support to gpgpusim. Allows for dynamically enabled print
+  streams. Currently the warp scheduler and scoreboard use this system.
+  All prints done after reading the configuration file should be moved to use
+  it.
   See the manual for details on how to use the system.
-- Added support in ptx_instruction to return a std::string which returns the ptx/ptxplus line.
+- Added support in ptx_instruction to return a std::string which returns the
+  ptx/ptxplus line.
 - Added a Greedy Then Oldest (GTO) warp scheduler
-  as described by Rogers et al.(Cache-Conscious Wavefront Scheduling - MICRO 45).
+  as described by Rogers et al.(Cache-Conscious Wavefront Scheduling
+  - MICRO 45).
 - Set the GTO scheduler as the default in the GTX480 configuration.
 - Bug Fixes:
     - Applied patch from Kito Cheng to update libopencl for checking NULL error
@@ -40,8 +52,8 @@ Version 3.2.0+edits (development branch) versus 3.2.0
       correctly independent of the system locale.
     - Fixed L2 Writeback bug caused by using the memory partition address for 
       both the cache set index generation and for storing tag/block address. 
-      Caused writebacks from the L2 to have a different address than the original 
-      memory request.
+      Caused writebacks from the L2 to have a different address than the
+      original memory request.
     - Fixed a number of warnings generated by gcc 4.7.x
     - Fixed a delete [] problem.
     - Fixed a potential issue memsetting *this to 0.
@@ -49,7 +61,10 @@ Version 3.2.0+edits (development branch) versus 3.2.0
     - The fix for Bug 42 uncovered a bug processing the special "null" register
       denoted by "_".  This has been fixed.
     - Fixed the implementation of the two level scheduler.
-      Previously testing if an instruction was dependent on a long latency operation was broken
+      Previously testing if an instruction was dependent on a long latency
+      operation was broken
+    - Fixed a bug in setup_enironment that trashed your LD_LIBRARY_PATH if
+      GPGPUSIM_ROOT was not the first entry in the list;.
 
 Version 3.2.0 versus 3.1.2
 - Added GPUWattch GPGPU power model based on McPAT 0.8beta. 
@@ -68,12 +83,13 @@ Version 3.1.2 versus 3.1.1
 - Added support for popc instruction. 
 - Changed ssy ptxplus instructions to have their own opcode but they still act
   as a nop right now.
-- Added support for converting BRX sass instructions to brx ptxplus instructions
-  in cuobjdump_to_ptxplus and started work on getting the brx ptxplus
-  instruction to work in gpgpusim.
-- Modified the cache hierarchy (cache_t -> baseline_cache -> [read_only_cache, data_cache, ...])
-- Enabled configurable cache policies (write-back, write-through) and implemented 
-  a write-allocate policy
+- Added support for converting BRX sass instructions to brx ptxplus
+  instructions in cuobjdump_to_ptxplus and started work on getting the brx
+  ptxplus instruction to work in gpgpusim.
+- Modified the cache hierarchy (cache_t -> baseline_cache -> [read_only_cache,
+  data_cache, ...])
+- Enabled configurable cache policies (write-back, write-through) and
+  implemented a write-allocate policy
 - Added functional execution support for shared memory atomic operations
 - Updated the option parser to support strings delimited by characters such as
   '=' and ';'.  This allow options with a long string of sub-options (e.g. DRAM
@@ -124,8 +140,9 @@ Version 3.1.2 versus 3.1.1
     - Fixed .loc directive parsing for PC-Histogram (CFLog) in AerialVision. 
 
 Version 3.1.1 versus 3.1.0
-- Add checks to top level makefile to ensure setup_environment is run and checks to
-  setup_environment to ensure a compatible version of CUDA is installed.
+- Add checks to top level makefile to ensure setup_environment is run and
+  checks to setup_environment to ensure a compatible version of CUDA is
+  installed.
 - Change Fermi configuration folder name to GTX480.
 - Added TeslaC2050 configuration.
 - Added a two level warp scheduler (as presented at ISCA 2012 tutorial).
@@ -137,9 +154,11 @@ Version 3.1.1 versus 3.1.0
 - Change cuobjdump_to_ptxplus to use std::string instead of char*.
 - Print out instructions at branch divergence/reconvergence points
 - Bug Fixes:
-    - SIMT stack correctly handles recursive functions by allocating a new stack entry on every
+    - SIMT stack correctly handles recursive functions by allocating a new
+      stack entry on every
       function call
-    - Fixed a bug in executing call_imp and callp_imp with the pure functional simulation mode.
+    - Fixed a bug in executing call_imp and callp_imp with the pure functional
+      simulation mode.
     - Fixed a couple of memory errors in cuobjdump_to_ptxplus code.
     - Implemented better support for handling memory operand type modifier
       in cuobjdump_to_ptxplus
@@ -191,11 +210,11 @@ Version 3.1.0 versus 3.0.2
 - Removed the no longer supported/used decuda_to_ptxplus
 - Removed all dependencies on the boost libraries. Now GPGPU-Sim can run
   without boost.
-- Added missing support for -gpgpu_perfect_mem. When enabled this option models 
-  a memory system with single cycle latency per memory request for accesses that 
-  miss in the L1 cache. Bandwidth is limited to one memory request issued per 
-  SIMT core cycle. Note this means uncoalesced accessess will be slower than 
-  coalesced accesses.
+- Added missing support for -gpgpu_perfect_mem. When enabled this option models
+  a memory system with single cycle latency per memory request for accesses
+  that miss in the L1 cache. Bandwidth is limited to one memory request issued
+  per SIMT core cycle. Note this means uncoalesced accessess will be slower
+  than coalesced accesses.
 - Bug Fixes:
     - Added a missed call to operand collector writeback which fixes some
       writebacks that were not considered by the operand collector.
@@ -209,12 +228,12 @@ Version 3.1.0 versus 3.0.2
       Atomic Operation Unit; atomic accesses now have a payload both to and
       from the Atomic Operation Unit
     - Fixed a bug that caused deadlock check to be omitted
-    - Updated the Fermi config files such that when an access misses the L1 data 
-      cache, it allocates a line immediately before sending a data fetch request 
-      out to the memory partition. 
-    - Changed the writeback arbitration among multiple clients in the LDST unit 
+    - Updated the Fermi config files such that when an access misses the L1
+      data cache, it allocates a line immediately before sending a data fetch
+      request out to the memory partition. 
+    - Changed the writeback arbitration among multiple clients in the LDST unit
       to round-robin. 
-    - Fixed a rare pathological case that caused LD instructions with divergent 
+    - Fixed a rare pathological case that caused LD instructions with divergent
       memory accesses to be overcounted.  
     - Fixed linear_to_raw_address_translation::partition_address() so that it 
       works for non-power-of-two number of memory partitions.  Before, it just 
diff --git a/setup_environment b/setup_environment
index c0f8b1f..cb39553 100644
--- a/setup_environment
+++ b/setup_environment
@@ -74,10 +74,10 @@ fi
 # against instead of the CUDA toolkit.  This replaces this cumbersome
 # static link setup in prior GPGPU-Sim releases.
 if [ `uname` = "Darwin" ]; then
-	export DYLD_LIBRARY_PATH=`echo $DYLD_LIBRARY_PATH | sed -Ee 's/.*gpgpu_sim.*(release|debug)://'`
+	export DYLD_LIBRARY_PATH=`echo $DYLD_LIBRARY_PATH | sed -Ee 's#'$GPGPUSIM_ROOT'\/lib\/[0-9]+\/(debug|release):##'`
 	export DYLD_LIBRARY_PATH=$GPGPUSIM_ROOT/lib/$GPGPUSIM_CONFIG:$DYLD_LIBRARY_PATH
 else
-	export LD_LIBRARY_PATH=`echo $LD_LIBRARY_PATH | sed -re 's/.*gpgpu_sim.*(release|debug)://'`
+	export LD_LIBRARY_PATH=`echo $LD_LIBRARY_PATH | sed -re 's#'$GPGPUSIM_ROOT'\/lib\/[0-9]+\/(debug|release):##'`
 	export LD_LIBRARY_PATH=$GPGPUSIM_ROOT/lib/$GPGPUSIM_CONFIG:$LD_LIBRARY_PATH
 fi