Need to make sure we don't kill the L1 too

5 files changed, 9 insertions, 1 deletions

diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config
index 31fbecb..857a0ff 100644
--- a/configs/Pascal-P100-HBM/gpgpusim.config
+++ b/configs/Pascal-P100-HBM/gpgpusim.config
@@ -55,6 +55,8 @@
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # Pascal GP100 has 64KB Shared memory
 -gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
 -gpgpu_shmem_size 65536
 -gpgpu_shmem_size_PrefL1 65536
 -gpgpu_shmem_size_PrefShared 65536
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config
index 8e1e56f..feb8c0b 100644
--- a/configs/Pascal-P102-GDDR5X/gpgpusim.config
+++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config
@@ -62,6 +62,8 @@
 # Pascal GP102 has 24KB L1 cache
 # The defulat is to disable the L1 cache, unless cache modifieres is used
 -gpgpu_cache:dl1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
index b87d958..a5e6736 100644
--- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
@@ -55,6 +55,8 @@
 # Pascal GP100 has 64KB Shared memory
 # Pascal GP100 has 48KB L1 cache
 -gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
 -gpgpu_shmem_size 65536
 -gpgpu_shmem_size_PrefL1 65536
 -gpgpu_shmem_size_PrefShared 65536
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
index 2df24e1..f78bd02 100644
--- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
@@ -56,6 +56,8 @@
 # Pascal GP102 has 64KB L1 cache
 # The defulat is to disable the L1 cache, unless cache modifieres is used
 -gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
 -gpgpu_shmem_size 98304
 -gpgpu_shmem_size_PrefL1 98304
 -gpgpu_shmem_size_PrefShared 98304
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 17f1714..bb448b3 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
                    "none" );
-    option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
+    option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
                    "per-shader L1 data cache config "
                    " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
                    "none" );