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authorAndrew M. B. Boktor <[email protected]>2012-02-22 12:26:47 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:19:03 -0700
commit4f2a7a85b94ea6ba2839c022d41369ac7062d050 (patch)
tree33b7e9cf4d72d08ec28a09caedd3aadae6d98850
parent1986cc83e77a5fab56d43922bc8375723d7427a2 (diff)
Cleaned up the comments I had in the configuration file
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11493]
-rw-r--r--configs/Fermi/gpgpusim.config16
1 files changed, 3 insertions, 13 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config
index accc49a..78df079 100644
--- a/configs/Fermi/gpgpusim.config
+++ b/configs/Fermi/gpgpusim.config
@@ -8,13 +8,12 @@
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 6
-# Fermi
+# Fermi clock domains
-gpgpu_clock_domains 700.0:700.0:700.0:3696.0
# shader core pipeline config
-gpgpu_shader_registers 32768
-# ask wilson about the next two lines
-gpgpu_shader_core_pipeline 1024:32:32
-gpgpu_shader_cta 16
-gpgpu_simd_model 1
@@ -22,24 +21,20 @@
# In Fermi, the cache and shared memory could be configured to 16kb:48kb or 48kb:16kb
# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
-# mysteriously gives much better correlation (and faster runs) than a configured cache
-#-gpgpu_cache:dl1 none
-gpgpu_cache:dl1 32:128:4:L:R:f,A:32:8,8
-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case more DL1 Cache is selected
#-gpgpu_cache:dl1 64:128:6:L:R:f,A:32:8,8
#-gpgpu_shmem_size 16384
# 256 sets, each 512 bits 6-way, this gives 786KB L2 cache
-# this entry gives slightly worse correlation that the quadro config
-gpgpu_cache:dl2 256:512:6:L:R:m,A:32:4,4
-#-gpgpu_cache:dl2 64:32:8:L:R:m,A:16:4,4
#-gpgpu_cache:dl2_texture_only
-gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4
-gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2
-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4
-#-gpgpu_tex_cache:l1 none
-#-gpgpu_const_cache:l1 none
-gpgpu_num_reg_banks 16
@@ -57,7 +52,6 @@
-gpgpu_n_mem_per_ctrlr 2
# for Fermi, bus width is 384bits, this is 24 bytes *2 because of double data rate
-# try if making the buswidth smaller affects the correlation, should try the memory frequency too
-gpgpu_dram_buswidth 24
-gpgpu_dram_burst_length 4
-gpgpu_mem_address_mask 1
@@ -66,10 +60,6 @@
# ANDREW
# GDDR5 timing from hynix H5GQ1H24AFR
# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}
-# CL and WL need to be figured out accurately
-# in the GDDR5 datasheet WL= min 3, max 7
-# I couldn't find tCDLR in the datasheet either, what does it mean? ask wilson may be
-# This configuration turns out to decrease the cpi correlation by about .03% for Fermi probably increases clk correlation
-gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12
# GDDR3