adding binary version and remove core id from the trace parsing

5 files changed, 234 insertions, 173 deletions

diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
index bcfa4eb..423019b 100644
--- a/src/trace-driven/trace_driven.cc
+++ b/src/trace-driven/trace_driven.cc
@@ -19,6 +19,8 @@
 #include "../../libcuda/gpgpu_context.h"
 #include "trace_driven.h"
 #include "trace_opcode.h"
+#include "volta_opcode.h"
+#include "turing_opcode.h"
 #include "../gpgpusim_entrypoint.h"
 
 
@@ -73,7 +75,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr
 	std::cout << "Processing kernel " <<kerneltraces_filepath<<std::endl;
 
 	unsigned grid_dim_x=0, grid_dim_y=0, grid_dim_z=0, tb_dim_x=0, tb_dim_y=0, tb_dim_z=0;
-	unsigned shmem=0, nregs=0, cuda_stream_id=0, kernel_id=0;
+	unsigned shmem=0, nregs=0, cuda_stream_id=0, kernel_id=0, binary_verion=0;
 	std::string line;
 	std::stringstream ss;
 	std::string string1, string2;
@@ -115,6 +117,9 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr
 			else if (string1 == "cuda" && string2 == "stream") {
 				sscanf(line.c_str(), "-cuda stream id = %d", &cuda_stream_id);
 			}
+			else if (string1 == "binary" && string2 == "version") {
+				sscanf(line.c_str(), "-binary version = %d", &binary_verion);
+			}
 			std::cout << line << std::endl;
 			continue;
 		}
@@ -127,7 +132,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr
 	dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z);
 	trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context);
 	function_info->set_name(kernel_name.c_str());
-	trace_kernel_info_t* kernel_info =  new trace_kernel_info_t(gridDim, blockDim, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context);
+	trace_kernel_info_t* kernel_info =  new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context);
 
 	return kernel_info;
 }
@@ -169,6 +174,19 @@ address_type trace_shd_warp_t::get_pc(){
 	return warp_traces[trace_pc].pc;
 }
 
+trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context):kernel_info_t(gridDim, blockDim, m_function_info) {
+	ifs = inputstream;
+	m_gpgpu_sim = gpgpu_sim;
+	m_gpgpu_context = gpgpu_context;
+	binary_verion = m_binary_verion;
+
+	//resolve the binary version
+	if(m_binary_verion == VOLTA_BINART_VERSION)
+		OpcodeMap = &Volta_OpcodeMap;
+	else
+		assert(0 && "unsupported binary version");
+}
+
 bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces) {
 
 	for(unsigned i=0; i<threadblock_traces.size(); ++i) {
@@ -225,7 +243,7 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
 			else {
 				assert(start_of_tb_stream_found);
 				trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context);
-				inst.parse_from_string(line);
+				inst.parse_from_string(line, OpcodeMap);
 				threadblock_traces[warp_id]->push_back(inst);
 			}
 		}
@@ -235,7 +253,7 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
 }
 
 
-bool trace_warp_inst_t::parse_from_string(std::string trace){
+bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap){
 
 	std::stringstream ss;
 	ss.str(trace);
@@ -257,7 +275,10 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 	int stride=0;
 
 	//Start Parsing
-	ss>>std::dec>>threadblock_x>>threadblock_y>>threadblock_z>>warpid_tb>>sm_id>>warpid_sm;
+	ss>>std::dec>>threadblock_x>>threadblock_y>>threadblock_z>>warpid_tb;
+
+	//ignore core id
+	//ss>>std::dec>>sm_id>>warpid_sm;
 
 	ss>>std::hex>>m_pc;
 	ss>>std::hex>>mask;
@@ -283,7 +304,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 
 	if(mem_width > 0)  //then it is a memory inst
 	{
-		ss>>std:dec>>address_mode;
+		ss>>std::dec>>address_mode;
 		if(address_mode==0){
 			//read addresses one by one from the file
 			for (int s = 0; s < warp_size(); s++) {
@@ -332,7 +353,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 			opcode_tokens.push_back(token);
 	}
 
-	std::string opcode1 = opcode.substr(0, opcode.find("."));
+	std::string opcode1 = opcode_tokens[0];
 
 	//fill and initialize common params
 	m_decoded = true;
@@ -355,8 +376,8 @@ bool trace_warp_inst_t::parse_from_string(std::string trace){
 	op = ALU_OP;
 	mem_op= NOT_TEX;
 
-	std::unordered_map<std::string,OpcodeChar>::const_iterator it= OpcodeMap.find(opcode1);
-	if (it != OpcodeMap.end()) {
+	std::unordered_map<std::string,OpcodeChar>::const_iterator it= OpcodeMap->find(opcode1);
+	if (it != OpcodeMap->end()) {
 		m_opcode = it->second.opcode;
 		op = (op_type)(it->second.opcode_category);
 	}
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
index 5e11448..47b7b30 100644
--- a/src/trace-driven/trace_driven.h
+++ b/src/trace-driven/trace_driven.h
@@ -9,6 +9,7 @@
 
 #include "../abstract_hardware_model.h"
 #include "../gpgpu-sim/shader.h"
+#include "trace_opcode.h"
 
 class trace_function_info: public function_info {
 public:
@@ -43,7 +44,7 @@ public:
 		m_opcode=0;
 	}
 
-	bool parse_from_string(std::string trace);
+	bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap);
 
 private:
 	void set_latency(unsigned cat);
@@ -53,11 +54,7 @@ private:
 
 class trace_kernel_info_t: public kernel_info_t {
 public:
-	trace_kernel_info_t(dim3 gridDim, dim3 blockDim, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context):kernel_info_t(gridDim, blockDim, m_function_info) {
-		ifs = inputstream;
-		m_gpgpu_sim = gpgpu_sim;
-		m_gpgpu_context = gpgpu_context;
-	}
+	trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context);
 
 	bool get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces);
 
@@ -65,6 +62,8 @@ private:
 	std::ifstream* ifs;
 	gpgpu_sim * m_gpgpu_sim;
 	gpgpu_context* m_gpgpu_context;
+	unsigned binary_verion;
+	const std::unordered_map<std::string,OpcodeChar>* OpcodeMap;
 
 };
 
diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h
index f0172e1..4e4abc7 100644
--- a/src/trace-driven/trace_opcode.h
+++ b/src/trace-driven/trace_opcode.h
@@ -59,163 +59,5 @@ struct OpcodeChar
 	unsigned opcode_category;
 };
 
-///Volta SM_70 ISA
-//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
-static const std::unordered_map<std::string,OpcodeChar> OpcodeMap = {
-		//Floating Point 32 Instructions
-		{"FADD", OpcodeChar(OP_FADD, SP_OP)},
-		{"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
-		{"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
-		{"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
-		{"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
-		{"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
-		{"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
-		{"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
-		{"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
-		{"FSET", OpcodeChar(OP_FSET, SP_OP)},
-		{"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
-		{"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
-		//SFU
-		{"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
-
-		//Floating Point 16 Instructions
-		{"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
-		{"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
-		{"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
-		{"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
-		{"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
-		{"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
-		{"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
-		{"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
-
-		//Tensor Core Instructions
-		{"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)},
-
-		//Double Point Instructions
-		{"DADD", OpcodeChar(OP_DADD, DP_OP)},
-		{"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
-		{"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
-		{"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
-
-		//Integer Instructions
-		{"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
-		{"BREV", OpcodeChar(OP_BREV, INTP_OP)},
-		{"FLO", OpcodeChar(OP_FLO, INTP_OP)},
-		{"IABS", OpcodeChar(OP_IABS, INTP_OP)},
-		{"IADD", OpcodeChar(OP_IADD, INTP_OP)},
-		{"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
-		{"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
-		{"IDP", OpcodeChar(OP_IDP, INTP_OP)},
-		{"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
-		{"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
-		{"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
-		{"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
-		{"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
-		{"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
-		{"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
-		{"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
-		{"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
-		{"LEA", OpcodeChar(OP_LEA, INTP_OP)},
-		{"LOP", OpcodeChar(OP_LOP, INTP_OP)},
-		{"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
-		{"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
-		{"POPC", OpcodeChar(OP_POPC, INTP_OP)},
-		{"SHF", OpcodeChar(OP_SHF, INTP_OP)},
-		{"SHR", OpcodeChar(OP_SHR, INTP_OP)},
-		{"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
-		{"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
-
-		//Conversion Instructions
-		{"F2F", OpcodeChar(OP_F2F, ALU_OP)},
-		{"F2I", OpcodeChar(OP_F2I, ALU_OP)},
-		{"I2F", OpcodeChar(OP_I2F, ALU_OP)},
-		{"I2I", OpcodeChar(OP_I2I, ALU_OP)},
-		{"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
-		{"FRND", OpcodeChar(OP_FRND, ALU_OP)},
-
-		//Movement Instructions
-		{"MOV", OpcodeChar(OP_MOV, ALU_OP)},
-		{"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
-		{"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
-		{"SEL", OpcodeChar(OP_SEL, ALU_OP)},
-		{"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
-		{"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
-
-		//Predicate Instructions
-		{"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
-		{"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
-		{"P2R", OpcodeChar(OP_P2R, ALU_OP)},
-		{"R2P", OpcodeChar(OP_R2P, ALU_OP)},
-
-		//Load/Store Instructions
-		{"LD", OpcodeChar(OP_LD, LOAD_OP)},
-		//For now, we ignore constant loads, consider it as ALU_OP, TO DO
-		{"LDC", OpcodeChar(OP_LDC, ALU_OP)},
-		{"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
-		{"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
-		{"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
-		{"ST", OpcodeChar(OP_ST, STORE_OP)},
-		{"STG", OpcodeChar(OP_STG, STORE_OP)},
-		{"STL", OpcodeChar(OP_STL, STORE_OP)},
-		{"STS", OpcodeChar(OP_STS, STORE_OP)},
-		{"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
-		{"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
-		{"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
-		{"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
-		{"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
-		{"RED", OpcodeChar(OP_RED, STORE_OP)},
-		{"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
-		{"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
-		{"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
-		{"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
-		{"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
-
-		//Texture Instructions
-		//For now, we ignore texture loads, consider it as ALU_OP
-		{"TEX", OpcodeChar(OP_TEX, ALU_OP)},
-		{"TLD", OpcodeChar(OP_TLD, ALU_OP)},
-		{"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
-		{"TMML", OpcodeChar(OP_TMML, ALU_OP)},
-		{"TXD", OpcodeChar(OP_TXD, ALU_OP)},
-		{"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
-
-		//Control Instructions
-		{"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)},
-		{"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
-		{"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
-		{"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)},
-		{"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
-		{"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)},
-		{"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)},
-		{"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
-		{"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
-		{"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
-		{"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
-		{"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
-		{"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
-		{"RET", OpcodeChar(OP_RET, RET_OPS)},
-		{"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)},
-		{"RTT", OpcodeChar(OP_RTT, RET_OPS)},
-		{"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)},
-		{"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)},
-
-		//Miscellaneous Instructions
-		{"B2R", OpcodeChar(OP_B2R, ALU_OP)},
-		{"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
-		{"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
-		{"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
-		{"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
-		{"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
-		{"LEPC", OpcodeChar(OP_LEPC ,ALU_OP)},
-		{"NOP", OpcodeChar(OP_NOP ,ALU_OP)},
-		{"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
-		{"R2B", OpcodeChar(OP_R2B, ALU_OP)},
-		{"S2R", OpcodeChar(OP_S2R, ALU_OP)},
-		{"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
-		{"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
-		{"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
-		{"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
-
-};
 
 #endif
diff --git a/src/trace-driven/turing_opcode.h b/src/trace-driven/turing_opcode.h
new file mode 100644
index 0000000..5fe9740
--- /dev/null
+++ b/src/trace-driven/turing_opcode.h
@@ -0,0 +1,24 @@
+
+
+#ifndef TURING_OPCODE_H
+#define TURING_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include "trace_opcode.h"
+#include <unordered_map>
+#include <string>
+
+//TO DO: moving this to a yml or def files
+
+
+#define TURING_BINART_VERSION 72
+
+///Tuing SM_72 ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<std::string,OpcodeChar> Turing_OpcodeMap = {
+
+//TO fill
+
+};
+
+#endif
diff --git a/src/trace-driven/volta_opcode.h b/src/trace-driven/volta_opcode.h
new file mode 100644
index 0000000..8de0775
--- /dev/null
+++ b/src/trace-driven/volta_opcode.h
@@ -0,0 +1,175 @@
+
+
+#ifndef VOLTA_OPCODE_H
+#define VOLTA_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include "trace_opcode.h"
+#include <unordered_map>
+#include <string>
+
+#define VOLTA_BINART_VERSION 70
+
+
+//TO DO: moving this to a yml or def files
+
+///Volta SM_70 ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<std::string,OpcodeChar> Volta_OpcodeMap = {
+		//Floating Point 32 Instructions
+		{"FADD", OpcodeChar(OP_FADD, SP_OP)},
+		{"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
+		{"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+		{"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
+		{"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+		{"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+		{"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+		{"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
+		{"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
+		{"FSET", OpcodeChar(OP_FSET, SP_OP)},
+		{"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+		{"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
+		//SFU
+		{"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
+
+		//Floating Point 16 Instructions
+		{"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
+		{"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
+		{"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
+		{"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
+		{"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
+		{"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
+		{"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
+		{"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
+
+		//Tensor Core Instructions
+		{"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)},
+
+		//Double Point Instructions
+		{"DADD", OpcodeChar(OP_DADD, DP_OP)},
+		{"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+		{"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+		{"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+		//Integer Instructions
+		{"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
+		{"BREV", OpcodeChar(OP_BREV, INTP_OP)},
+		{"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+		{"IABS", OpcodeChar(OP_IABS, INTP_OP)},
+		{"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+		{"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
+		{"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
+		{"IDP", OpcodeChar(OP_IDP, INTP_OP)},
+		{"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
+		{"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+		{"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
+		{"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+		{"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+		{"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
+		{"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+		{"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
+		{"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+		{"LEA", OpcodeChar(OP_LEA, INTP_OP)},
+		{"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+		{"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
+		{"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
+		{"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+		{"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+		{"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+		{"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
+		{"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
+
+		//Conversion Instructions
+		{"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+		{"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+		{"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+		{"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+		{"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
+		{"FRND", OpcodeChar(OP_FRND, ALU_OP)},
+
+		//Movement Instructions
+		{"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+		{"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+		{"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+		{"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+		{"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
+		{"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+		//Predicate Instructions
+		{"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
+		{"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+		{"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+		{"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+
+		//Load/Store Instructions
+		{"LD", OpcodeChar(OP_LD, LOAD_OP)},
+		//For now, we ignore constant loads, consider it as ALU_OP, TO DO
+		{"LDC", OpcodeChar(OP_LDC, ALU_OP)},
+		{"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+		{"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+		{"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+		{"ST", OpcodeChar(OP_ST, STORE_OP)},
+		{"STG", OpcodeChar(OP_STG, STORE_OP)},
+		{"STL", OpcodeChar(OP_STL, STORE_OP)},
+		{"STS", OpcodeChar(OP_STS, STORE_OP)},
+		{"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
+		{"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
+		{"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+		{"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
+		{"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
+		{"RED", OpcodeChar(OP_RED, STORE_OP)},
+		{"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+		{"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+		{"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
+		{"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+		{"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
+
+		//Texture Instructions
+		//For now, we ignore texture loads, consider it as ALU_OP
+		{"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+		{"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+		{"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+		{"TMML", OpcodeChar(OP_TMML, ALU_OP)},
+		{"TXD", OpcodeChar(OP_TXD, ALU_OP)},
+		{"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+		//Control Instructions
+		{"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)},
+		{"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+		{"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+		{"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)},
+		{"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+		{"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)},
+		{"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)},
+		{"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
+		{"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
+		{"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+		{"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+		{"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
+		{"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
+		{"RET", OpcodeChar(OP_RET, RET_OPS)},
+		{"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)},
+		{"RTT", OpcodeChar(OP_RTT, RET_OPS)},
+		{"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)},
+		{"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)},
+
+		//Miscellaneous Instructions
+		{"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+		{"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+		{"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
+		{"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
+		{"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
+		{"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
+		{"LEPC", OpcodeChar(OP_LEPC ,ALU_OP)},
+		{"NOP", OpcodeChar(OP_NOP ,ALU_OP)},
+		{"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
+		{"R2B", OpcodeChar(OP_R2B, ALU_OP)},
+		{"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+		{"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
+		{"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
+		{"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+		{"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
+
+};
+
+#endif