diff options
| author | Mahmoud <[email protected]> | 2018-10-17 20:34:30 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-10-17 20:34:30 -0400 |
| commit | 5e7f41f4f66fa2fad5326a0429293b083481182c (patch) | |
| tree | d66942a3e66a675b43e63ee38cebda5a2e98afad | |
| parent | e41955fb2b2041c67f5a4a5627d4870c4cda13aa (diff) | |
updating CHANGES, version and README files
| -rw-r--r-- | CHANGES | 29 | ||||
| -rw-r--r-- | README | 15 | ||||
| -rw-r--r-- | version | 2 |
3 files changed, 45 insertions, 1 deletions
@@ -1,4 +1,33 @@ LOG: +Version 3.3.0 (development branch) versus 3.2.3 +-Front-End: +1- Support .nc cache modifier and __ldg function to access the read-only L1D cache +2- Partially-support some SASS_60 in the PTXP_PLUs (not completede yet) +-GPU Core: +1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors. +2- Adding separate dp, int and tenssor unit pipeline. +3- diff dual issue: allow scheduler to issue diff insts at a time +4- Fair memory issue from multiple schedulers. +-Cache System: +1- Sector L1/L2 cache +2- Fetch-on-write and lazy-fetch-on-read write allocation policy. +3- Improving the L1 cache throughput (streaming L1 cache) +4- Performance model for CUDA memory copy. +5- Support memory partition indexing to reduce partition camping (POLY, XOR and PAE (ISCA’18) Indexing) +6- Adaptive cache configuration +-Memory: +1- Performance Model for HBM (mainly the dual-bus interface) +2- Separate Read/Write buffers. +3- Advanced bank indexing function. +-Statistics: +1- Adding more detailed cache statistics to define and analyze cache bottlenecks. +2- Adding more detailed memory statistics (BLP, RBL, etc) to define and analyze memory bottlenecks. +-Configs: +Adding the Pascal and Volta config files that has been correlated against real hardware. +See the correlation website here: +https://engineering.purdue.edu/tgrogers/group/correlator.html + + Version 3.2.3+edits (development branch) versus 3.2.3 - Support for running regression tests using Travis - Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech) @@ -18,6 +18,11 @@ Analyzing CUDA Workloads Using a Detailed GPU Simulator, in IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, MA, April 19-21, 2009. +If you use GPGPU-Sim 3.3 version in your research, please cite: +Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers, +" Exploring Modern GPU Memory System Design Challenges through Accurate Modeling", arXiv:1810.07269, +https://arxiv.org/abs/1810.07269 + If you use the GPUWattch energy model in your research, please cite: Jingwen Leng, Tayler Hetherington, Ahmed ElTantawy, Syed Gilani, Nam Sung Kim, @@ -38,6 +43,16 @@ Complex Dynamics in Many-Core Accelerator Architectures, In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 164-174, White Plains, NY, March 28-30, 2010. +On-progress work (to be released soon): +Currently, we extensivly update our gpgpu-sim infrastructure. This contains: +1- Change the Functional model to be trace-driven-based and support the moden machine Pascal SASS 6.0 ISA. +2- Adding Volta Core model (including the Tensor Core support) +3- Supporting Nvidia dev libraries (CuBLAS, CUDNN, etc) +4- Supporting NUMA multi-chip GPU systems. +5- Heterogeneous memory support (HBM, NVRAM and GDDR5X) +6- Integrating with SST infrastructure. +7- Updating and improving the accuracy the GPUWATTCH to model Pascal and Volta. + This file contains instructions on installing, building and running GPGPU-Sim. Detailed documentation on what GPGPU-Sim models, how to configure it, and a guide to the source code can be found here: <http://gpgpu-sim.org/manual/>. @@ -1 +1 @@ -const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.2.2 "; +const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.3.0 "; |
