Ejection from the interface buffer between interconnet and L2 happens in L2 clock domain instead of ICNT clock domain.

Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled.
cuda regression tests pass

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]

1 files changed, 11 insertions, 11 deletions

diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 988806c..10fadb7 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -811,20 +811,20 @@ void gpgpu_sim::cycle()
 
    // L2 operations follow L2 clock domain
    if (clock_mask & L2) {
-      for (unsigned i=0;i<m_memory_config->m_n_mem;i++) 
-         m_memory_partition_unit[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
+      for (unsigned i=0;i<m_memory_config->m_n_mem;i++) {
+          //move memory request from interconnect into memory partition (if not backed up)
+          //Note:This needs to be called in DRAM clock domain if there is no L2 cache in the system
+          if ( m_memory_partition_unit[i]->full() ) {
+             gpu_stall_dramfull++;
+          } else {
+              mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
+              m_memory_partition_unit[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
+          }
+          m_memory_partition_unit[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
+      }
    }
 
    if (clock_mask & ICNT) {
-      for (unsigned i=0;i<m_memory_config->m_n_mem;i++) {
-         if ( m_memory_partition_unit[i]->full() ) {
-            gpu_stall_dramfull++;
-            continue;
-         }
-         // move memory request from interconnect into memory partition (if memory controller not backed up)
-         mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
-         m_memory_partition_unit[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
-      }
       icnt_transfer();
    }