Merge branch 'dev' into fix-stats

54 files changed, 4327 insertions, 207 deletions

diff --git a/aerialvision/configs.py b/aerialvision/configs.py
index f0389ac..01dba2e 100644
--- a/aerialvision/configs.py
+++ b/aerialvision/configs.py
@@ -61,7 +61,7 @@
 # Vancouver, BC V6T 1Z4
 
 
-import ConfigParser, os
+import configparser, os
 
 userSettingPath = os.path.join(os.environ['HOME'], '.gpgpu_sim', 'aerialvision')
 
@@ -69,14 +69,14 @@ userSettingPath = os.path.join(os.environ['HOME'], '.gpgpu_sim', 'aerialvision')
 class AerialVisionConfig:
 
     def __init__(self):
-        self.config = ConfigParser.SafeConfigParser()
+        self.config = configparser.SafeConfigParser()
         self.config.read( os.path.join(userSettingPath, 'config.rc') )
 
     def print_all(self):
         for section in self.config.sections():
             for option in self.config.options(section):
                 value = self.config.get(section, option)
-                print "\t%s.%s = %s" % (section, option, value);
+                print("\t%s.%s = %s" % (section, option, value));
 
     def get_value(self, section, option, default):
         if (self.config.has_option(section, option)):
@@ -90,10 +90,11 @@ avconfig = AerialVisionConfig()
 
 #Unit test / configviewer
 def main():
-    print "AerialVision Options:"
+    print("AerialVision Options:")
     avconfig.print_all()
-    print "";
+    print("");
 
 if __name__ == "__main__":
     main()
 
+
diff --git a/aerialvision/guiclasses.py b/aerialvision/guiclasses.py
index 04036a8..f4ecd29 100644
--- a/aerialvision/guiclasses.py
+++ b/aerialvision/guiclasses.py
@@ -64,10 +64,10 @@
 import time
 import os
 import array
-import Tkinter as Tk
+import tkinter as Tk
 import matplotlib
 matplotlib.use('TkAgg')
-from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2TkAgg
+from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2Tk
 from matplotlib.figure import Figure
 import matplotlib as mpl
 from matplotlib.colors import colorConverter
@@ -250,19 +250,19 @@ class formEntry:
     self.cXAxisData.delete(0, Tk.END)
     self.cYAxisData.delete(0, Tk.END)
     
-    
+      
     #filling in xAxis vars
-    for keys in self.data[self.fileChosen].keys():
+    for keys in list(self.data[self.fileChosen].keys()):
         if keys == 'globalCycle':
             self.cXAxisData.insert(Tk.END, keys)
             
     #filling in yAxis vars
     #Need to fill up list alphabetically
     keysAlpha = []
-    for key in self.data[self.fileChosen].keys():
+    for key in list(self.data[self.fileChosen].keys()):
         if key not in ['globalCycle','CFLOG','EXTVARS']:#exclude hacks from list
             keysAlpha.append(key)
-    keysAlpha.sort(lambda x, y: cmp(x.lower(),y.lower()))
+    #keysAlpha.sort(key=lambda x, y: cmp(x.lower(),y.lower()))
     for keys in keysAlpha:
         self.cYAxisData.insert(Tk.END, keys)
             
@@ -782,7 +782,7 @@ class graphManager:
         #self.plot = self.figure.add_subplot(111)
         self.canvas = FigureCanvasTkAgg(self.figure, master=self.graphArea)
         self.canvas.get_tk_widget().pack()
-        self.toolbar = NavigationToolbar2TkAgg(self.canvas, self.toolbarArea)
+        self.toolbar = NavigationToolbar2Tk(self.canvas, self.toolbarArea)
         self.toolbar.update()
         self.plotData()
         
@@ -931,7 +931,7 @@ class graphManager:
         
         
         
-        if self.simplerName.has_key('globalTotInsn') == 'False':
+        if ('globalTotInsn' in self.simplerName) == 'False':
             graphOption = 1
             
         if (graphOption == 1):  
@@ -972,7 +972,7 @@ class graphManager:
 
         graphOption = "NULL"
             
-        if self.simplerName.has_key('globalTotInsn') == 'False':
+        if ('globalTotInsn' in self.simplerName) == 'False':
             graphOption = 1
     
         if (graphOption == 1):
@@ -1018,7 +1018,7 @@ class graphManager:
     
         #if there are kernals.. we need to adjust the x axis for proper labelling
         #Need to make changes here.. works for now though
-        if self.simplerName.has_key('globalTotInsn'):
+        if 'globalTotInsn' in self.simplerName:
             x = self.updateVarKernal(x)
 
         concentrationFactor = len(x) // 512 + 1
@@ -1038,7 +1038,7 @@ class graphManager:
         yoff = numpy.array([0.0] * numCols) #variable use to remember the last top location of a bar so that we may stack the proceeding bar on top of it
         #Legendname = ['UNUSED', 'UNUSED', 'FQPUSHED','ICNT_PUSHED','ICNT_INJECTED','ICNT_AT_DEST','DRAMQ','DRAM_PROCESSING_START','DRAM_PROCESSING_END','DRAM_OUTQ','2SH_ICNT_PUSHED','2SH_ICNT_INJECTED','2SH_ICNT_AT_DEST','2SH_FQ_POP','RETURN_Q']; 
         Legendname = ['N/A', 'N/A','N/A','IcntInpBuf','N/A','Icnt2DRAM','N/A','N/A','N/A','DRAM','2Sh_IcntInpBuf','N/A','Icnt2shd','N/A','N/A']; 
-        BarSequence = range(numRows-1,-1,-1)
+        BarSequence = list(range(numRows-1,-1,-1))
 
         if yAxis == 'WarpDivergenceBreakdown':
             Legendname = []
@@ -1046,21 +1046,21 @@ class graphManager:
             Legendname.append('Data Hazard')
             Legendname.append('Stall')
             for c in range(2, numRows):
-                Legendname.append('W' + `4*(c-2)+1` +  ':' + `4*(c-1)`)
-            BarSequence = range(0,numRows)
+                Legendname.append('W' + repr(4*(c-2)+1) +  ':' + repr(4*(c-1)))
+            BarSequence = list(range(0,numRows))
 
         if yAxis == 'WarpIssueSlotBreakdown':
             Legendname = []
             for c in range(0, numRows):
-                Legendname.append('W' + `c`)
-            BarSequence = range(0,numRows)
+                Legendname.append('W' + repr(c))
+            BarSequence = list(range(0,numRows))
 
         dynamic_warp_resolution = 32
         if yAxis == 'WarpIssueDynamicIdBreakdown':
             Legendname = []
             for c in range(0, numRows):
-                Legendname.append('W' + `dynamic_warp_resolution*c` + ":" + `dynamic_warp_resolution*(c+1)`)
-            BarSequence = range(0,numRows)
+                Legendname.append('W' + repr(dynamic_warp_resolution*c) + ":" + repr(dynamic_warp_resolution*(c+1)))
+            BarSequence = list(range(0,numRows))
 
         yoff_max = numpy.array([0.0] * numCols)
         for row in range(numRows-1,-1,-1):
@@ -1102,10 +1102,10 @@ class graphManager:
         for label in self.plot.get_yticklabels():
             label.set_fontsize(plotFormat.yticksFontSize)
      
-        self.canvas.show()
+        self.canvas.draw()
         
     def type4Variable(self, x, xAxis, y, yAxis, plotID):
-        keys = y.keys()
+        keys = list(y.keys())
         keys.sort()
             
         if (self.dataPointer.graphChosen == self.possGraphs[3]):
@@ -1251,7 +1251,7 @@ class graphManager:
       self.plot.set_title(self.plotFormatInfo[self.currPlot].title)
       self.plot.set_xlabel(self.plotFormatInfo[self.currPlot].xlabel, fontsize = self.plotFormatInfo[self.currPlot].labelFontSize)
       self.plot.set_ylabel(self.plotFormatInfo[self.currPlot].ylabel, fontsize = self.plotFormatInfo[self.currPlot].labelFontSize)
-      self.canvas.show()
+      self.canvas.draw()
     
     
     def plotMultVarLine(self, x, xAxis, y, yAxis):
@@ -1261,7 +1261,7 @@ class graphManager:
       self.plotFormatInfo[self.currPlot].InitLabels(xlabel = xAxis, ylabel = yAxis, cbarlabel = '', title = '')
       self.plot.set_xlabel(self.plotFormatInfo[self.currPlot].xlabel, fontsize = self.plotFormatInfo[self.currPlot].labelFontSize)
       self.plot.set_ylabel(self.plotFormatInfo[self.currPlot].ylabel, fontsize = self.plotFormatInfo[self.currPlot].labelFontSize)
-      self.canvas.show()
+      self.canvas.draw()
 
 
     def plotScatter(self, x, xAxis, y, yAxis, plotID):
@@ -1275,7 +1275,7 @@ class graphManager:
         self.plot.set_title(plotFormat.title, fontsize = plotFormat.labelFontSize)
         self.plot.set_xlabel(plotFormat.xlabel, fontsize = plotFormat.labelFontSize)
         self.plot.set_ylabel(plotFormat.ylabel, fontsize = plotFormat.labelFontSize)
-        self.canvas.show()
+        self.canvas.draw()
       
     
     def takeDerivativeMult(self,x,y):
@@ -1347,12 +1347,12 @@ class graphManager:
         
         # put number on axis if there are more than one ticks 
         if (self.xAxisStepsWilStack[self.currPlot] != 1):
-            for count in range(0,len(x),len(x)/self.xAxisStepsWilStack[self.currPlot]):
+            for count in range(0,len(x),int(len(x)/self.xAxisStepsWilStack[self.currPlot])):
                 xlabelValues.append(x[count])
                 xlabelPos.append(xticksPos[count])
         
-        print self.yAxisStepsWilStack[self.currPlot]
-        for count in range(0,len(y),len(y)/self.yAxisStepsWilStack[self.currPlot]):
+        print(self.yAxisStepsWilStack[self.currPlot])
+        for count in range(0,len(y),int(len(y)/self.yAxisStepsWilStack[self.currPlot])):
             ylabelValues.append(yTicks[count])
             ylabelPos.append(yticksPos[count])            
 
@@ -1387,7 +1387,7 @@ class graphManager:
         xtickStep = x[1] - x[0]
         self.plot.set_xlim(0 / xtickStep - 0.5, self.xlim / xtickStep + 0.5)
 
-        self.canvas.show()
+        self.canvas.draw()
         
     def updateWilTicks(self, z):
         x= []
@@ -1480,7 +1480,7 @@ class graphManager:
                   else:
                       for iter in range(0, self.dataPointer.dydx):
                         if self.simplerName[self.dataPointer.dataChosenY].type == 4:
-                          keys = self.simplerName[self.dataPointer.dataChosenY].data.keys()
+                          keys = list(self.simplerName[self.dataPointer.dataChosenY].data.keys())
                           keys.sort()
                           y = []
                           for iter in keys:
@@ -1523,7 +1523,7 @@ class graphManager:
               entry[self.currPlot] = (maxEntry, minEntry)
         
               cmap = self.plotFormatInfo[self.currPlot].cmap
-              plotCMap = apply(Tk.OptionMenu, (root[-1], cmap) + tuple(PlotFormatInfo.cmapOptions)) 
+              plotCMap = Tk.OptionMenu(*(root[-1], cmap) + tuple(PlotFormatInfo.cmapOptions)) 
               plotCMap.pack(side = Tk.LEFT, padx = 5)
           
 
@@ -1612,7 +1612,7 @@ class graphManager:
         for self.currPlot in range(1,numPlots + 1):
           self.findKernalLocs()
           
-          if vars.has_key(str(self.currPlot)):
+          if str(self.currPlot) in vars:
               if vars[str(self.currPlot)].get() == 1:
                   self.dataPointer.dydx += 1
 
@@ -1681,12 +1681,12 @@ class graphManager:
         if (self.yAxisStepsWilStack[plotToIncrease] == 1):
             self.yAxisStepsWilStack[plotToIncrease] = 2
         self.yAxisStepsWilStack[plotToIncrease] = int(float(self.yAxisStepsWilStack[plotToIncrease])*1.50)
-        print self.yAxisStepsWilStack[plotToIncrease]
+        print(self.yAxisStepsWilStack[plotToIncrease])
         self.plotDataForNewBinning(plotToIncrease)
 
     def collectDataDecreaseYBinning(self, currPlot, remove = False):
         plotToDecrease = int(currPlot[0])
-        print self.yAxisStepsWilStack[plotToDecrease]
+        print(self.yAxisStepsWilStack[plotToDecrease])
         if (remove == True):
             self.yAxisStepsWilStack[plotToDecrease] = 1
         else:
@@ -1751,7 +1751,7 @@ class graphManager:
           entries[self.currPlot].append(Tk.Entry(root, width = 50))
           entries[self.currPlot][-1].grid(row = currentRow, column = 4, padx = 10)
           entries[self.currPlot][-1].insert(0, self.plot.get_xlabel())
-          if self.colorbars.has_key(self.currPlot):
+          if self.currPlot in self.colorbars:
               plotLabel3 = Tk.Label(root, text = 'Colorbar: ', bg = 'white')
               plotLabel3.grid(row = currentRow, column = 5)
               entries[self.currPlot].append(Tk.Entry(root, width = 20))
@@ -1821,7 +1821,7 @@ class graphManager:
           self.plot.set_ylabel(plotFormat.ylabel, fontsize=plotFormat.labelFontSize)
           plotFormat.xlabel = entries[self.currPlot][1].get()
           self.plot.set_xlabel(plotFormat.xlabel, fontsize=plotFormat.labelFontSize)
-          if self.colorbars.has_key(self.currPlot):
+          if self.currPlot in self.colorbars:
               plotFormat.cbarlabel = entries[self.currPlot][2].get()
               self.colorbars[self.currPlot].set_label(plotFormat.cbarlabel, fontsize=plotFormat.labelFontSize)
           else:
@@ -1841,7 +1841,7 @@ class graphManager:
               ytickslabels[n].set_fontsize(plotFormat.yticksFontSize)
 
           # change colorbar ticks label fontsize
-          if self.colorbars.has_key(self.currPlot):
+          if self.currPlot in self.colorbars:
               for label in self.colorbars[self.currPlot].ax.get_yticklabels():
                   label.set_fontsize(plotFormat.cticksFontSize)
 
@@ -1851,7 +1851,7 @@ class graphManager:
         
         master.destroy()
         ## Now replot with changes.....
-        self.canvas.show()
+        self.canvas.draw()
 
     def zoomButton(self):
         #Variable initializations
@@ -1980,7 +1980,7 @@ class graphManager:
                     plot.set_xticks(xlabelPos)
 
         master.destroy()
-        self.canvas.show()
+        self.canvas.draw()
     
 
 class NaviPlotInfo:
@@ -2224,6 +2224,7 @@ class newTextTab:
         
         countLines = 1
         for lines in self.file.readlines():
+            lines = lines.decode()
             self.textbox.insert(Tk.END, str(countLines) + '.   ' + lines, ('normal'))
             countLines += 1
         countLines -= 1
@@ -2232,7 +2233,7 @@ class newTextTab:
         figure = Figure(figsize=(22,5), dpi = 70)
         self.histArea = FigureCanvasTkAgg(figure, master= bottomFrame)
         self.histArea.get_tk_widget().pack()
-        toolbar  = NavigationToolbar2TkAgg(self.histArea, toolbarFrame)
+        toolbar  = NavigationToolbar2Tk(self.histArea, toolbarFrame)
         toolbar.update()
         self.histogram = figure.add_subplot(111)
         cid = figure.canvas.mpl_connect('button_press_event',self.onclick)
@@ -2285,8 +2286,8 @@ class newTextTab:
             count += 1
 
     def yview(self, *args):
-        apply(self.textbox.yview, args)
-        apply(self.statstextbox.yview, args)
+        self.textbox.yview(*args)
+        self.statstextbox.yview(*args)
         
     def onclick(self, event):
       if event.button == 3:
@@ -2298,6 +2299,7 @@ class newTextTab:
         self.textbox.delete(0.0, Tk.END)
         self.file = open(self.fileChosen, 'r')
         for lines in self.file.readlines():
+          lines=lines.decode()
           if (countLines < event.xdata - 1) or (countLines > event.xdata + 1):
             self.textbox.insert(Tk.END, str(countLines) + '.   ' + lines, ('normal'))
           else:
@@ -2317,8 +2319,8 @@ class newTextTab:
           
         
         
-        apply(self.textbox.yview, args)
-        apply(self.statstextbox.yview, args)
+        self.textbox.yview(*args)
+        self.statstextbox.yview(*args)
       
     def chooseFileCuda(self, *event):
       self.fileChosen = self.cAvailableCudaFiles.get('active')
@@ -2572,3 +2574,4 @@ class newTextTab:
             
             
         
+
diff --git a/aerialvision/lexyacc.py b/aerialvision/lexyacc.py
index d657383..53541ed 100644
--- a/aerialvision/lexyacc.py
+++ b/aerialvision/lexyacc.py
@@ -82,7 +82,7 @@ def import_user_defined_variables(variables):
     try:
         file = open(os.path.join(userSettingPath, 'variables.txt'),'r')
     except:
-        print "No variables.txt file found."
+        print("No variables.txt file found.")
         return
 
     #this can be replaced with a proper lex-yacc parser later
@@ -96,7 +96,7 @@ def import_user_defined_variables(variables):
                 continue
 
             # parse the line containing definition of a stat variable
-            s = line.split(",")
+            s = line.split(',')
             statName = s[0]
             statVar = vc.variable('', 1, 0)
             statVar.importFromString(line)
@@ -104,8 +104,9 @@ def import_user_defined_variables(variables):
             # add parsed stat variable to the searchable map
             variables[statName] = statVar
             
-        except Exception, (e):
-            print "error:",e,", in variables.txt line:",line
+        except Exception as xxx_todo_changeme:
+            (e) = xxx_todo_changeme
+            print("error:",e,", in variables.txt line:",line)
 
 # Parses through a given log file for data
 def parseMe(filename):
@@ -136,7 +137,7 @@ def parseMe(filename):
         t.lexer.lineno += t.value.count("\n")
         
     def t_error(t):
-        print "Illegal character '%s'" % t.value[0]
+        print("Illegal character '%s'" % t.value[0])
         t.lexer.skip(1) 
 
     lex.lex()
@@ -202,14 +203,14 @@ def parseMe(filename):
 
     # generate a lookup table based on the specified name in log file for each stat
     stat_lookuptable = {}
-    for name, var in variables.iteritems():
+    for name, var in variables.items():
         if (name == 'CFLOG'):
             continue;
         if (var.lookup_tag != ''):
             stat_lookuptable[var.lookup_tag] = var 
         else:
             stat_lookuptable[name.lower()] = var
-    
+
     inputData = 'NULL'
 
     # a table containing all the metrics that has received the missing data warning 
@@ -218,19 +219,19 @@ def parseMe(filename):
     def p_sentence(p):
         '''sentence : WORD NUMBERSEQUENCE'''
         #print p[0], p[1],p[2]
-        num = p[2].split(" ")  
+        num = p[2].split(' ')  
         
         # detect empty data entry for particular metric and print a warning 
         if p[2] == '': 
             if not p[1] in stat_missing_warned: 
-                print "WARNING: Sample entry for metric '%s' has no data. Skipping..." % p[1]
+                print("WARNING: Sample entry for metric '%s' has no data. Skipping..." % p[1])
                 stat_missing_warned[p[1]] = True
             return
 
         lookup_input = p[1].lower()
         if (lookup_input  in stat_lookuptable):
             if (lookup_input == "globalcyclecount") and (int(num[0]) % 10000 == 0):
-                print "Processing global cycle %s" % num[0]
+                print("Processing global cycle %s" % num[0])
                 
             stat = stat_lookuptable[lookup_input]
             if (stat.type == 1):
@@ -294,7 +295,7 @@ def parseMe(filename):
 
     def p_error(p):
         if p:
-            print("Syntax error at '%s'" % p.value)
+            print(("Syntax error at '%s'" % p.value))
         else:
             print("Syntax error at EOF")
     
@@ -306,11 +307,12 @@ def parseMe(filename):
     else:
         file = open(filename, 'r')
     while file:
-        line = file.readline()
+        line = file.readline().decode()
+
         if not line : break
-        nameNdata = line.split(":")
+        nameNdata = line.split(':')
         if (len(nameNdata) != 2): 
-            print("Syntax error at '%s'" % line) 
+            print(("Syntax error at '%s'" % line)) 
         namePart = nameNdata[0].strip()
         dataPart= nameNdata[1].strip()
         parts = [' ', namePart, dataPart]
@@ -323,3 +325,4 @@ def parseMe(filename):
 
 
 
+
diff --git a/aerialvision/lexyaccbookmark.py b/aerialvision/lexyaccbookmark.py
index 42c6b40..7aa2f80 100644
--- a/aerialvision/lexyaccbookmark.py
+++ b/aerialvision/lexyaccbookmark.py
@@ -108,7 +108,7 @@ def parseMe():
 
         
     def t_error(t):
-        print "Illegal character '%s'" % t.value[0]
+        print("Illegal character '%s'" % t.value[0])
         t.lexer.skip(1) 
     
     lex.lex()    
@@ -150,7 +150,7 @@ def parseMe():
             pass
 
         else:
-            print 'An Parsing Error has occurred'
+            print('An Parsing Error has occurred')
             
 
     
@@ -159,7 +159,7 @@ def parseMe():
 
     def p_error(p):
         if p:
-            print("Syntax error at '%s'" % p.value)
+            print(("Syntax error at '%s'" % p.value))
         else:
             print("Syntax error at EOF")
     
@@ -168,7 +168,7 @@ def parseMe():
     try:
         file = open(os.environ['HOME'] + '/.gpgpu_sim/aerialvision/bookmarks.txt', 'r')
         inputData = file.readlines()
-    except IOError,e:
+    except IOError as e:
         if e.errno == 2:
             inputData = ''
         else:
@@ -178,3 +178,4 @@ def parseMe():
         yacc.parse(x[0:-1]) # ,debug=True)
         
     return listBookmarks
+
diff --git a/aerialvision/lexyacctexteditor.py b/aerialvision/lexyacctexteditor.py
index 51d3ced..57b41db 100644
--- a/aerialvision/lexyacctexteditor.py
+++ b/aerialvision/lexyacctexteditor.py
@@ -88,7 +88,7 @@ def textEditorParseMe(filename):
         t.lexer.lineno += t.value.count("\n")
         
     def t_error(t):
-        print "Illegal character '%s'" % t.value[0]
+        print("Illegal character '%s'" % t.value[0])
         t.lexer.skip(1)
         
     lex.lex()
@@ -109,8 +109,8 @@ def textEditorParseMe(filename):
 
     def p_error(p):
       if p:
-          print("Syntax error at '%s'" % p.value)
-          print p
+          print(("Syntax error at '%s'" % p.value))
+          print(p)
       else:
           print("Syntax error at EOF")
 
@@ -152,17 +152,18 @@ def ptxToCudaMapping(filename):
       loc = int(m.group(2))
 
     count += 1
-  x = map.keys()
+  x = list(map.keys())
   return map
     
 
 #Unit test / playground
 def main():
     data = textEditorParseMe(sys.argv[1])
-    print data[100]
+    print(data[100])
    
 if __name__ == "__main__":
     main()
   
   
   
+
diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py
index 090b90f..f5d5312 100644
--- a/aerialvision/organizedata.py
+++ b/aerialvision/organizedata.py
@@ -99,7 +99,7 @@ def organizedata(fileVars):
     }
     data_type_char = {int:'I', float:'f'}
 
-    print "Organizing data into internal format..."
+    print("Organizing data into internal format...")
 
     # Organize globalCycle in advance because it is used as a reference
     if ('globalCycle' in fileVars):
@@ -107,28 +107,28 @@ def organizedata(fileVars):
         fileVars['globalCycle'].data = organizeFunction[statData.organize](statData.data, data_type_char[statData.datatype])
 
     # Organize other stat data into internal format
-    for statName, statData in fileVars.iteritems():
+    for statName, statData in fileVars.items():
         if (statName != 'CFLOG' and statName != 'globalCycle' and statData.organize != 'custom'):
             fileVars[statName].data = organizeFunction[statData.organize](statData.data, data_type_char[statData.datatype])
   
     # Custom routines to organize stat data into internal format
-    if fileVars.has_key('averagemflatency'):
+    if 'averagemflatency' in fileVars:
         zeros = []
         for count in range(len(fileVars['averagemflatency'].data),len(fileVars['globalCycle'].data)):
             zeros.append(0)
         fileVars['averagemflatency'].data = zeros + fileVars['averagemflatency'].data
 
-    if (skipCFLog == 0) and fileVars.has_key('CFLOG'):
+    if (skipCFLog == 0) and 'CFLOG' in fileVars:
         ptxFile = CFLOGptxFile
         statFile = CFLOGInsnInfoFile
         
-        print "PC Histogram to CUDA Src = %d" % convertCFLog2CUDAsrc
+        print("PC Histogram to CUDA Src = %d" % convertCFLog2CUDAsrc)
         parseCFLOGCUDA = convertCFLog2CUDAsrc
 
         if parseCFLOGCUDA == 1:
-            print "Obtaining PTX-to-CUDA Mapping from %s..." % ptxFile
+            print("Obtaining PTX-to-CUDA Mapping from %s..." % ptxFile)
             map = lexyacctexteditor.ptxToCudaMapping(ptxFile.rstrip())
-            print "Obtaining Program Range from %s..." % statFile
+            print("Obtaining Program Range from %s..." % statFile)
             maxStats = max(lexyacctexteditor.textEditorParseMe(statFile.rstrip()).keys())
 
         if parseCFLOGCUDA == 1:
@@ -136,7 +136,7 @@ def organizedata(fileVars):
             for lines in map:
                 for ptxLines in map[lines]:
                     newMap[ptxLines] = lines
-            print "    Total number of CUDA src lines = %s..." % len(newMap)
+            print("    Total number of CUDA src lines = %s..." % len(newMap))
             
             markForDel = []
             for ptxLines in newMap:
@@ -144,7 +144,7 @@ def organizedata(fileVars):
                     markForDel.append(ptxLines)
             for lines in markForDel:
                 del newMap[lines]
-            print "    Number of touched CUDA src lines = %s..." % len(newMap)
+            print("    Number of touched CUDA src lines = %s..." % len(newMap))
     
         fileVars['CFLOGglobalPTX'] = vc.variable('',2,0)
         fileVars['CFLOGglobalCUDA'] = vc.variable('',2,0)
@@ -152,7 +152,7 @@ def organizedata(fileVars):
         count = 0
         for iter in fileVars['CFLOG']:
 
-            print "Organizing data for %s" % iter
+            print("Organizing data for %s" % iter)
 
             fileVars[iter + 'PTX'] = fileVars['CFLOG'][iter]
             fileVars[iter + 'PTX'].data = CFLOGOrganizePTX(fileVars['CFLOG'][iter].data, fileVars['CFLOG'][iter].maxPC)
@@ -174,7 +174,7 @@ def organizedata(fileVars):
                             for columns in range(0, len(fileVars[iter + 'CUDA'].data[rows])): 
                                 fileVars['CFLOGglobalCUDA'].data[rows][columns] += fileVars[iter + 'CUDA'].data[rows][columns]
             except:
-                print "Error in generating globalCFLog data"
+                print("Error in generating globalCFLog data")
 
             count += 1
         del fileVars['CFLOG']
@@ -231,10 +231,10 @@ def nullOrganizedStackedBar(nullVar, datatype_c):
         for row in range (0,len(organized)):
             newy = array.array(datatype_c, [0 for col in range(newLen)])
             for col in range(0, len(organized[row])):
-                newcol = col / n_data
+                newcol = int(col / n_data)
                 newy[newcol] += organized[row][col]
             for col in range(0, len(newy)):
-                newy[col] /= n_data 
+                newy[col] = int(newy[col]/n_data) 
             organized[row] = newy
 
     return organized
@@ -320,15 +320,15 @@ def CFLOGOrganizeCuda(list, ptx2cudamap):
     nSamples = len(list[0])
 
     # create a dictionary of empty data array (one array per cuda source line)
-    for ptxline, cudaline in ptx2cudamap.iteritems():
-        if tmp.has_key(cudaline):
+    for ptxline, cudaline in ptx2cudamap.items():
+        if cudaline in tmp:
             pass
         else:
             tmp[cudaline] = [0 for lengthData in range(nSamples)]
 
 
     for cudaline in tmp:
-        for ptxLines, mapped_cudaline in ptx2cudamap.iteritems():
+        for ptxLines, mapped_cudaline in ptx2cudamap.items():
             if mapped_cudaline == cudaline:
                 for lengthData in range(nSamples):
                     tmp[cudaline][lengthData] += list[ptxLines][lengthData]
@@ -336,7 +336,7 @@ def CFLOGOrganizeCuda(list, ptx2cudamap):
     
     final = []           
     for iter in range(min(tmp.keys()),max(tmp.keys())):
-        if tmp.has_key(iter):
+        if iter in tmp:
             final.append(tmp[iter])            
         else:
             final.append([0 for lengthData in range(nSamples)])
@@ -356,3 +356,4 @@ def CFLOGOrganizeCuda(list, ptx2cudamap):
 #    return organized
 
 
+
diff --git a/aerialvision/parser.out b/aerialvision/parser.out
new file mode 100644
index 0000000..809874f
--- /dev/null
+++ b/aerialvision/parser.out
@@ -0,0 +1,47 @@
+Created by PLY version 3.11 (http://www.dabeaz.com/ply)
+
+Grammar
+
+Rule 0     S' -> sentence
+Rule 1     sentence -> WORD NUMBERSEQUENCE
+
+Terminals, with rules where they appear
+
+NUMBERSEQUENCE       : 1
+WORD                 : 1
+error                : 
+
+Nonterminals, with rules where they appear
+
+sentence             : 0
+
+Parsing method: LALR
+
+state 0
+
+    (0) S' -> . sentence
+    (1) sentence -> . WORD NUMBERSEQUENCE
+
+    WORD            shift and go to state 2
+
+    sentence                       shift and go to state 1
+
+state 1
+
+    (0) S' -> sentence .
+
+
+
+state 2
+
+    (1) sentence -> WORD . NUMBERSEQUENCE
+
+    NUMBERSEQUENCE  shift and go to state 3
+
+
+state 3
+
+    (1) sentence -> WORD NUMBERSEQUENCE .
+
+    $end            reduce using rule 1 (sentence -> WORD NUMBERSEQUENCE .)
+
diff --git a/aerialvision/parsetab.py b/aerialvision/parsetab.py
new file mode 100644
index 0000000..47a3884
--- /dev/null
+++ b/aerialvision/parsetab.py
@@ -0,0 +1,31 @@
+
+# parsetab.py
+# This file is automatically generated. Do not edit.
+# pylint: disable=W,C,R
+_tabversion = '3.10'
+
+_lr_method = 'LALR'
+
+_lr_signature = 'NUMBERSEQUENCE WORDsentence : WORD NUMBERSEQUENCE'
+    
+_lr_action_items = {'WORD':([0,],[2,]),'$end':([1,3,],[0,-1,]),'NUMBERSEQUENCE':([2,],[3,]),}
+
+_lr_action = {}
+for _k, _v in _lr_action_items.items():
+   for _x,_y in zip(_v[0],_v[1]):
+      if not _x in _lr_action:  _lr_action[_x] = {}
+      _lr_action[_x][_k] = _y
+del _lr_action_items
+
+_lr_goto_items = {'sentence':([0,],[1,]),}
+
+_lr_goto = {}
+for _k, _v in _lr_goto_items.items():
+   for _x, _y in zip(_v[0], _v[1]):
+       if not _x in _lr_goto: _lr_goto[_x] = {}
+       _lr_goto[_x][_k] = _y
+del _lr_goto_items
+_lr_productions = [
+  ("S' -> sentence","S'",1,None,None,None),
+  ('sentence -> WORD NUMBERSEQUENCE','sentence',2,'p_sentence','lexyacc.py',220),
+]
diff --git a/aerialvision/startup.py b/aerialvision/startup.py
index ae14fd3..d261c0c 100644
--- a/aerialvision/startup.py
+++ b/aerialvision/startup.py
@@ -62,11 +62,11 @@
 
 
 import sys
-import Tkinter as Tk
+import tkinter as Tk
 import Pmw
 import lexyacc
 import guiclasses
-import tkFileDialog as Fd
+import tkinter.filedialog as Fd
 import organizedata
 import os
 import os.path
@@ -160,7 +160,7 @@ def fileInput(cl_files=None):
         tmprecentfile = tmprecentfile.split('/')
         for iter in range(1,len(tmprecentfile) - 1):
             recentfile = recentfile + '/' + tmprecentfile[iter]
-    except IOError,e:
+    except IOError as e:
         if e.errno == 2:
             # recentfiles.txt does not exist, ignore and use CWD
             recentfile = '.'
@@ -313,7 +313,7 @@ def loadRecentFile(entry):
     try: 
         loadfile = open(os.path.join(userSettingPath, 'recentfiles.txt'), 'r')
         recentfiles = loadfile.readlines()
-    except IOError,e:
+    except IOError as e:
         if e.errno == 2:
             recentfiles = ''
         else:
@@ -323,7 +323,7 @@ def loadRecentFile(entry):
     recentFileWindow.pack(side = Tk.TOP)
     scrollbar = Tk.Scrollbar(recentFileWindow, orient = Tk.VERTICAL)
     cRecentFile = Tk.Listbox(recentFileWindow, width = 100, height = 15, yscrollcommand = scrollbar.set)
-    cRecentFile.bind("<Double-Button-1>", lambda(event): recentFileInsert(entry, cRecentFile.get('active'), instance))
+    cRecentFile.bind("<Double-Button-1>", lambda event: recentFileInsert(entry, cRecentFile.get('active'), instance))
     cRecentFile.pack(side = Tk.LEFT)
     scrollbar.config(command = cRecentFile.yview)
     scrollbar.pack(side = Tk.LEFT, fill = Tk.Y)
@@ -391,9 +391,9 @@ def addListToListbox(listbox,list):
                 Filenames.append(string)
                 listbox.insert(Tk.END, string)
             else:
-                print 'Could not open file: ' + string
+                print('Could not open file: ' + string)
         except:
-            print 'Could not open file: ' + file
+            print('Could not open file: ' + file)
             
         
 def errorMsg(string):
@@ -447,6 +447,7 @@ def submitClicked(instance, num, skipcflog, cflog2cuda, listboxes):
     startup(res, [TEFiles, TEPTXFiles, TEStatFiles])
 
 def graphAddTab(vars, graphTabs,res, entry):
+
     
     TabsForGraphs.append(guiclasses.formEntry(graphTabs, str(len(TabsForGraphs) + 1), vars, res, entry))
     entry.delete(0, Tk.END)
@@ -586,7 +587,7 @@ def startup(res, TEFILES):
     organizedata.setCFLOGInfoFiles(TEFILES)
     for files in Filenames:
         vars[files] = organizedata.organizedata(vars[files])
-
+    
     graphAddTab(vars, graphTabs, res, eAddTab)
 
 
@@ -873,3 +874,4 @@ def manageFilesSubmit(window, listbox):
 
             
     
+
diff --git a/aerialvision/variableclasses.py b/aerialvision/variableclasses.py
index 18850a1..30d8d2d 100644
--- a/aerialvision/variableclasses.py
+++ b/aerialvision/variableclasses.py
@@ -102,8 +102,9 @@ class variable:
                 assert(self.organize == 'idx2DVec')
             elif (self.type == 5):
                 assert(self.organize == 'sparse')
-        except Exception, (e):
-            print "Error in creating new stat variable from string: %s" % string_spec
+        except Exception as xxx_todo_changeme:
+            (e) = xxx_todo_changeme
+            print("Error in creating new stat variable from string: %s" % string_spec)
             raise e
 
     def initSparseMatrix(self):
@@ -133,7 +134,7 @@ def loadLineStatName(filename):
     global lineStatName
     file = open(filename, 'r')
     while file:
-        line = file.readline()
+        line = file.readline().decode()
         if not line : break
         if (line.startswith('kernel line :')) :
             line = line.strip()
@@ -171,7 +172,7 @@ class cudaLineNo:
         except:
             tmp = 0
             if cudaLineNo.debug:
-                print 'Exception in cudaLineNo.takeMax()', self.stats[key]
+                print('Exception in cudaLineNo.takeMax()', self.stats[key])
         return tmp
         
     def takeRatioSums(self, key1,key2):
@@ -182,9 +183,9 @@ class cudaLineNo:
             return tmp1/tmp2
         except:
             if cudaLineNo.debug:
-                print tmp1, tmp2
+                print(tmp1, tmp2)
             if tmp2 == 0 and cudaLineNo.debug:
-                print 'infinite'
+                print('infinite')
             return 0
     
         
@@ -209,7 +210,7 @@ class ptxLineNo:
             return tmp1/tmp2
         except:
             if tmp2 == 0 and ptxLineNo.debug:
-                print 'infinite'
+                print('infinite')
             return 0
             
     
@@ -221,3 +222,4 @@ class ptxLineNo:
     
     
     
+
diff --git a/bin/aerialvision.py b/bin/aerialvision.py
index a5b02f0..5cc7ad9 100755
--- a/bin/aerialvision.py
+++ b/bin/aerialvision.py
@@ -66,20 +66,21 @@ import sys
 import os
 
 if not os.environ['HOME']:
-	print 'please set your HOME environment variable to your home directory'
+	print('please set your HOME environment variable to your home directory')
 	sys.exit
 if not os.environ['GPGPUSIM_ROOT']:
-	print 'please set your GPGPUSIM_ROOT environment variable to your home directory'
+	print('please set your GPGPUSIM_ROOT environment variable to your home directory')
 	sys.exit
 
 sys.path.append( os.environ['GPGPUSIM_ROOT'] + '/aerialvision/' ) 
 
-import Tkinter as Tk
+import tkinter as Tk
 import Pmw
 import startup
 import time
 
-from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2TkAgg
+from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2Tk
 from matplotlib.figure import Figure
 
 startup.fileInput(sys.argv[1:])
+
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 609a9ef..bc01821 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -56,7 +56,7 @@
 
 
 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 -gpgpu_cache:dl1  N:32:128:4,L:L:m:N:H,S:64:8,8
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
index c83159f..ef47ddf 100644
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -99,7 +99,7 @@
 # Greedy then oldest scheduler
 -gpgpu_scheduler gto
 
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # The defulat is to disable the L1 cache, unless cache modifieres are used
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 652f0a0..7d3e2d4 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -123,7 +123,7 @@
 -gpgpu_dual_issue_diff_exec_units 1
 
 ## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # The defulat is to disable the L1 cache, unless cache modifieres are used
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index 158b97e..6ff4b6c 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -83,7 +83,7 @@
 -gpgpu_dual_issue_diff_exec_units 1
 
 ## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # In adaptive cache, we adaptively assign the remaining shared memory to L1 cache 
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
diff --git a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
index 89435a9..08ac752 100644
--- a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
@@ -128,7 +128,7 @@
 -gpgpu_num_reg_banks 16
 -gpgpu_reg_file_port_throughput 2
 
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 -gpgpu_adaptive_cache_config 0
 -gpgpu_l1_banks 4
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim.xml
new file mode 100644
index 0000000..d94d5bd
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim.xml
@@ -0,0 +1,623 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="2" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="4.57" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="11.44089762" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="21.76302498" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="7.737353491" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="8.618027871" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="0.53469516" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="13.9055689" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="0.65916315" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="0.73418985" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="1.313660815" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0.053279375" /> <!--Register Reads-->

+		<param name="REG_WR" value="0.079919063" /> <!--Register Writes-->

+		<param name="INT_ACC" value="3.429666768" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.711591276" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="0.742812382" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.148636575" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.212559571" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="1.241271438" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.59034036" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.212555149" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.702043615" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.282564496" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="2.485" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="0.212559047" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.02772" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.0336" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.00924" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="1.046834662" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="2.670605032" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="3.269555394" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="2.18020968" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="83.18977901" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="0.0257" /> <!--Pipeline Accesses-->

+

+		<!-- PTX Model specific DYNAMIC Power Activity Factors-->

+

+		<param name="TC_H" value="0.01021" /> <!--Texture Cache Hits-->

+		<param name="TC_M" value="0.02466" /> <!--Texture Cache Misses-->

+		<param name="INT_MUL24_ACC" value="0.290770573" /> <!--Integer 24-bit MUL Accesses-->

+		<param name="INT_MUL32_ACC" value="0.252598514" /> <!--Integer 32-bit MUL Accesses-->

+		<param name="INT_DIV_ACC" value="5.121706665" /> <!--Integer DIV Accesses-->

+		<param name="FP_DIV_ACC" value="4.599926258" /> <!--FP DIV Accesses-->

+		<param name="DP_DIV_ACC" value="25.84876211" /> <!--DP DIV Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim_alt.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim_alt.xml
new file mode 100644
index 0000000..0c6f211
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_ptx_sim_alt.xml
@@ -0,0 +1,623 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="2" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="4.57" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="8.827711067" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="8.827711067" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="8.545163843" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="8.545163843" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="8.545163843" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="8.545163843" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="0.65916315" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="0.73418985" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="1.763326296" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0.126123699" /> <!--Register Reads-->

+		<param name="REG_WR" value="0.126123699" /> <!--Register Writes-->

+		<param name="INT_ACC" value="2.851008299" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.723984758" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="0.723979435" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.119939033" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.147036868" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="1.234782354" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.594393568" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.147037283" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.920933945" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.18425577" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="1.656666667" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="0.147036868" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.03058335" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.03058335" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.03058335" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="2.032318132" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="2.032318132" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="2.032318132" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="2.032318132" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="70.15055938" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="0.01" /> <!--Pipeline Accesses-->

+

+		<!-- PTX Model specific DYNAMIC Power Activity Factors-->

+

+		<param name="TC_H" value="0.1" /> <!--Texture Cache Hits-->

+		<param name="TC_M" value="0.1" /> <!--Texture Cache Misses-->

+		<param name="INT_MUL24_ACC" value="0.235290825" /> <!--Integer 24-bit MUL Accesses-->

+		<param name="INT_MUL32_ACC" value="0.250616643" /> <!--Integer 32-bit MUL Accesses-->

+		<param name="INT_DIV_ACC" value="5.327155759" /> <!--Integer DIV Accesses-->

+		<param name="FP_DIV_ACC" value="4.992722677" /> <!--FP DIV Accesses-->

+		<param name="DP_DIV_ACC" value="26.46013946" /> <!--DP DIV Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hw.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hw.xml
new file mode 100644
index 0000000..64f89d6
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hw.xml
@@ -0,0 +1,613 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="100" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="43.5416637" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="0" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="0" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="7.193244877" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="8.01198819" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="0.497094158" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="12.9276971" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="9.322047" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="10.383093" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="4.146674883" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0" /> <!--Register Reads-->

+		<param name="REG_WR" value="0" /> <!--Register Writes-->

+		<param name="INT_ACC" value="3.350646078" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.041043127" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="0.077722905" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.147866461" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.147864271" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="0.48526506" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.147864519" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.376510619" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.147862451" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.147865348" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="0.148632914" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="3.4530026" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.020752854" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.025154975" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.006917618" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="3.430442278" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="6.514812193" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="11.22265896" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="3.32662057" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="87.30828879" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="1.028" /> <!--Pipeline Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hybrid.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hybrid.xml
new file mode 100644
index 0000000..175f1fd
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_hybrid.xml
@@ -0,0 +1,613 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="100" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="48.259994" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="0" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="0" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="6.607568654" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="7.359649633" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="0.456620598" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="11.87512" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="5.932232271" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="6.607445701" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="5.116439734" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0" /> <!--Register Reads-->

+		<param name="REG_WR" value="0" /> <!--Register Writes-->

+		<param name="INT_ACC" value="7.725550311" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.201142468" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="0.201146878" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.130624774" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.130623287" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="0.195089274" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.130617842" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.202205086" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.130621909" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.130622532" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="0.240811904" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="3.453002628" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.01527021" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.018509345" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.00509007" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="3.391355385" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="6.440581599" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="11.09478657" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="3.288716634" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="86.3134871" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="0.514" /> <!--Pipeline Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim.xml
new file mode 100644
index 0000000..570332d
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim.xml
@@ -0,0 +1,613 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="10" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="4.661" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="8.593489331" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="29.735231" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="9.835033124" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="10.95446778" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="0.679656761" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="17.67551799" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="0.1107" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="0.1233" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="0.779992642" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0.100560581" /> <!--Register Reads-->

+		<param name="REG_WR" value="0.140604679" /> <!--Register Writes-->

+		<param name="INT_ACC" value="14.98768151" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.529670751" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="0.777229051" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.115098047" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.089517055" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="0.195089274" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.125521663" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.13336307" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.36204415" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.1321288" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="0.815454621" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="0.115100088" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.025941068" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.031443719" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.008647023" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="1.260867526" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="2.394535301" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="4.124916" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="1.222707601" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="32.09037703" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="0.514" /> <!--Pipeline Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim_alt.xml b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim_alt.xml
new file mode 100644
index 0000000..9998e96
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/accelwattch_sass_sim_alt.xml
@@ -0,0 +1,613 @@
+<?xml version="1.0" ?>

+<component id="root" name="root">

+	<component id="system" name="system">

+<!-- Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas

+Northwestern University, Purdue University, The University of British Columbia

+All rights reserved.

+

+Redistribution and use in source and binary forms, with or without

+modification, are permitted provided that the following conditions are met:

+

+1. Redistributions of source code must retain the above copyright notice, this

+   list of conditions and the following disclaimer;

+2. Redistributions in binary form must reproduce the above copyright notice,

+   this list of conditions and the following disclaimer in the documentation

+   and/or other materials provided with the distribution;

+3. Neither the names of Northwestern University, Purdue University,

+   The University of British Columbia nor the names of their contributors

+   may be used to endorse or promote products derived from this software

+   without specific prior written permission.

+

+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+POSSIBILITY OF SUCH DAMAGE. -->

+

+		<!-- DYNAMIC Power Activity Factors -->

+

+		<param name="TOT_INST" value="16" /> <!--Instruction Buffer Activity Factor(Total Warp Instructions)-->

+		<param name="FP_INT" value="2" /> <!--Scheduler Activity Factor(Non-Memory Warp Instructons)-->

+		<param name="IC_H" value="9.967097889" /> <!--Instruction Cache Hits -->

+		<param name="IC_M" value="9.967097889" /> <!--Instruction Cache Misses-->

+		<param name="DC_RH" value="9.382262155" /> <!--L1 Data Cache Read Hits--> 

+		<param name="DC_RM" value="9.382262155" /> <!--L1 Data Cache Read Misses-->

+		<param name="DC_WH" value="9.382262155" /> <!--L1 Data Cache Write Hits-->

+		<param name="DC_WM" value="9.382262155" /> <!--L1 Data Cache Write Misses-->

+		<param name="CC_H" value="0.5" /> <!--Constant Cache Hits-->

+		<param name="CC_M" value="0.5" /> <!--Constant Cache Misses-->

+		<param name="SHRD_ACC" value="1.045696662" /> <!--Shared Memory Accesses-->

+		<param name="REG_RD" value="0.096144789" /> <!--Register Reads-->

+		<param name="REG_WR" value="0.134430479" /> <!--Register Writes-->

+		<param name="INT_ACC" value="18.18093465" /> <!--Integer ALU Accesses-->

+		<param name="FP_ACC" value="0.810674358" /> <!--FPU Accesses-->

+		<param name="DP_ACC" value="1.061592439" /> <!--Integer Accesses-->

+		<param name="INT_MUL_ACC" value="0.114254558" /> <!--Integer MUL Accesses-->

+		<param name="FP_MUL_ACC" value="0.155989373" /> <!--FP MUL Accesses-->

+		<param name="FP_SQRT_ACC" value="0.377990392" /> <!--SFU: sqrt Accesses-->

+		<param name="FP_LG_ACC" value="0.155990168" /> <!--SFU: log Accesses-->

+		<param name="FP_SIN_ACC" value="0.155991536" /> <!--SFU: sin/cos Accesses-->

+		<param name="FP_EXP_ACC" value="0.571396061" /> <!--SFU: exponent Accesses-->

+		<param name="DP_MUL_ACC" value="0.155989896" /> <!--DP MUL Accesses-->

+		<param name="TENSOR_ACC" value="1.013271823" /> <!--Tensor Accesses-->

+		<param name="TEX_ACC" value="0.167780179" /> <!--Texture Unit Accesses-->

+		<param name="MEM_RD" value="0.032236806" /> <!--DRAM Reads-->

+		<param name="MEM_WR" value="0.032236806" /> <!--DRAM Writes-->

+		<param name="MEM_PRE" value="0.032236806" /> <!--DRAM Precharge-->

+		<param name="L2_RH" value="1.175516289" /> <!--L2 Data Cache Read Hits--> 

+		<param name="L2_RM" value="1.175516289" /> <!--L2 Data Cache Read Misses-->

+		<param name="L2_WH" value="1.175516289" /> <!--L2 Data Cache Write Hits-->

+		<param name="L2_WM" value="1.175516289" /> <!--L2 Data Cache Write Misses-->

+		<param name="NOC_A" value="77.25" /> <!--Interconnect Network Accesses-->

+		<param name="PIPE_A" value="0.4" /> <!--Pipeline Accesses-->

+

+		<!-- STATIC & CONSTANT Power -->

+

+		<param name="constant_power" value="32.32522272" /> <!--Constant power-->

+		<param name="idle_core_power" value="0.28279166"/> <!--Idle SM power-->

+

+		<param name="static_cat1_flane" value="15.29035866"/> <!--INT (ADD+MUL) First Lane Activation Power-->

+		<param name="static_cat1_addlane" value="0.586233603"/> <!--INT (ADD+MUL) Additional Lane Activation Power-->

+

+		<param name="static_cat2_flane" value="18.6179906"/> <!--INT+FP First Lane Activation Power-->

+		<param name="static_cat2_addlane" value="0.645228013"/> <!--INT+FP Additional Lane Activation Power-->

+

+		<param name="static_cat3_flane" value="19.10017723"/> <!--INT+FP+DP First Lane Activation Power-->

+		<param name="static_cat3_addlane" value="0.726863055"/> <!--INT+FP+DP Additional Lane Activation Power-->

+

+		<param name="static_cat4_flane" value="18.55029744"/> <!--INT+FP+SFU First Lane Activation Power-->

+		<param name="static_cat4_addlane" value="0.6099397"/> <!--INT+FP+SFU Additional Lane Activation Power-->

+

+		<param name="static_cat5_flane" value="14.74826681"/> <!--INT+FP+TEX First Lane Activation Power-->

+		<param name="static_cat5_addlane" value="0.514367937"/> <!--INT+FP+TEX Additional Lane Activation Power-->

+

+		<param name="static_cat6_flane" value="48.94875596"/> <!--INT+FP+TENSOR First Lane Activation Power-->

+		<param name="static_cat6_addlane" value="0.0"/> <!--INT+FP+TENSOR Additional Lane Activation Power-->

+

+		<param name="static_light_flane" value="1.965373811"/> <!--LIGHT_SM First Lane Activation Power-->

+		<param name="static_light_addlane" value="0.003966868"/> <!--LIGHT_SM Additional Lane Activation Power-->

+

+		<param name="static_intadd_flane" value="19.70468506"/> <!--INT ADD First Lane Activation Power-->

+		<param name="static_intadd_addlane" value="0.388578623"/> <!--INT ADD Additional Lane Activation Power-->

+

+		<param name="static_intmul_flane" value="16.64811823"/> <!--INT MUL First Lane Activation Power-->

+		<param name="static_intmul_addlane" value="0.281803166"/> <!--INT MUL Additional Lane Activation Power-->

+

+		<param name="static_geomean_flane" value="17.21745077"/> <!--GEOMEAN First Lane Activation Power-->

+		<param name="static_geomean_addlane" value="0.650630555"/> <!--GEOMEAN Additional Lane Activation Power-->		

+		<param name="static_shared_flane" value="31.40965691"/> <!--Shared Memory First Lane Activation Power-->

+		<param name="static_l1_flane" value="34.79491352"/> <!--L1D First Lane Activation Power-->

+		<param name="static_l2_flane" value="17.30654755"/> <!--L2D ADD+MUL First Lane Activation Power-->

+

+

+		<!-- LEAVE BELOW UNCHANGED! These are parameters used for initial GPUWattch model left untouched -->

+

+

+		<param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->

+		<param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->

+		<param name="number_of_L1Directories" value="0"/>

+		<param name="number_of_L2Directories" value="0"/>

+		<param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->

+		<param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->

+		<param name="number_of_NoCs" value="1"/> 

+		<param name="homogeneous_cores" value="1"/><!--1 means homo -->

+		<param name="homogeneous_L2s" value="1"/>

+		<param name="homogeneous_L1Directorys" value="1"/>

+		<param name="homogeneous_L2Directorys" value="1"/>

+		<param name="homogeneous_L3s" value="1"/>

+		<param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->

+		<param name="homogeneous_NoCs" value="1"/>

+		<param name="core_tech_node" value="23"/><!-- nm -->

+

+		<param name="number_cache_levels" value="2"/>

+		<param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->

+		<param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power)  -->

+		<param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->

+		<param name="machine_bits" value="32"/>

+		<param name="virtual_address_width" value="32"/>

+		<param name="physical_address_width" value="32"/>

+		<param name="virtual_memory_page_size" value="4096"/>

+

+		<param name="IDLE_CORE_N" value="1"/>

+		<stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->

+		<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		<stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		<stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 

+			virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank  -->

+		<!-- *********************** cores ******************* -->

+		<component id="system.core0" name="core0">

+			<!-- Core property -->

+			<param name="clock_rate" value="700"/>

+			<param name="instruction_length" value="32"/>

+			<param name="opcode_width" value="9"/>

+			<!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 

+			default value is machine_bits, if not set --> 

+			<param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->

+			<!-- inorder/OoO -->

+			<param name="number_hardware_threads" value="32"/>

+			<!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,

+			it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 

+			branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 

+			<param name="fetch_width" value="1"/>

+			<!-- fetch_width determins the size of cachelines of L1 cache block -->

+			<param name="number_instruction_fetch_ports" value="1"/>

+			<param name="decode_width" value="1"/>

+			<!-- decode_width determins the number of ports of the 

+			renaming table (both RAM and CAM) scheme -->

+			<param name="issue_width" value="2"/>

+			<!-- issue_width determins the number of ports of Issue window and other logic 

+			as in the complexity effective proccessors paper; issue_width==dispatch_width -->

+			<param name="commit_width" value="2"/>

+			<!-- commit_width determins the number of ports of register files -->

+			<param name="fp_issue_width" value="1"/>

+			<param name="prediction_width" value="0"/> 

+			<!-- number of branch instructions can be predicted simultannouesl-->

+			<!-- Current version of McPAT does not distinguish int and floating point pipelines 

+			Theses parameters are reserved for future use.--> 

+			<param name="pipelines_per_core" value="1,1"/>

+			<!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->

+			<param name="pipeline_depth" value="8,8"/>

+			<!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->

+			<!-- issue and exe unit-->

+			<param name="ALU_per_core" value="32"/>

+			<!-- contains an adder, a shifter, and a logical unit -->

+			<param name="MUL_per_core" value="4"/>

+			<!-- For MUL and Div -->

+			<param name="FPU_per_core" value="32"/>		

+			<!-- buffer between IF and ID stage -->

+			<param name="instruction_buffer_size" value="1"/>

+			<!-- buffer between ID and sche/exe stage -->

+			<param name="decoded_stream_buffer_size" value="1"/>

+			<param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->

+			<!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->

+			<param name="instruction_window_size" value="1"/>

+			<param name="fp_instruction_window_size" value="1"/>

+			<!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->

+			<param name="ROB_size" value="0"/>

+			<!-- each in-flight instruction has an entry in ROB -->

+			<!-- registers -->

+			<!-- SM parameters  Added by Syed Gilani -->

+			<param name="rf_banks" value="32"/>

+			<param name="simd_width" value="32"/>

+			<param name="collector_units" value="32"/>

+			<param name="core_clock_ratio" value="2"/>

+			<param name="warp_size" value="32"/>

+

+			<param name="archi_Regs_IRF_size" value="65536"/>			

+			<param name="archi_Regs_FRF_size" value="32"/>

+			<!--  if OoO processor, phy_reg number is needed for renaming logic, 

+			renaming logic is for both integer and floating point insts.  -->

+			<param name="phy_Regs_IRF_size" value="32"/>

+			<param name="phy_Regs_FRF_size" value="32"/>

+			<!-- rename logic -->

+			<param name="rename_scheme" value="0"/>

+			<!-- can be RAM based(0) or CAM based(1) rename scheme 

+			RAM-based scheme will have free list, status table;

+			CAM-based scheme have the valid bit in the data field of the CAM 

+			both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;

+			Detailed RAT Implementation see TR -->

+			<param name="register_windows_size" value="0"/>

+			<!-- how many windows in the windowed register file, sun processors;

+			no register windowing is used when this number is 0 -->

+			<!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),

+			They will always try to exeute out-of-order though. -->

+			<param name="LSU_order" value="inorder"/>

+			<param name="store_buffer_size" value="32"/>

+			<!-- By default, in-order cores do not have load buffers -->

+			<param name="load_buffer_size" value="32"/>	

+			<!-- number of ports refer to sustainable concurrent memory accesses --> 

+			<param name="memory_ports" value="2"/>	

+			<!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer

+			as well as the ports of Dcache which is connected to LSU -->	

+			<!-- dual-pumped Dcache can be used to save the extra read/write ports -->

+			<param name="RAS_size" value="1"/>						

+			<!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check  -->

+			<!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->

+			<stat name="total_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="branch_instructions" value="branch_instruction_match_mcpat"/>

+			<stat name="branch_mispredictions" value="0"/>

+			<stat name="load_instructions" value="load_instruction_match_mcpat"/>

+			<stat name="store_instructions" value="store_instruction_match_mcpat"/>

+			<stat name="committed_instructions" value="total_instructions_match_mcpat"/>

+			<stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>

+			<stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>

+			<stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->

+			<!-- the following cycle stats are used for heterogeneouse cores only, 

+				please ignore them if homogeneouse cores -->

+			<stat name="total_cycles" value="total_cycles_match_mcpat"/>

+		    <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>

+		    <stat name="busy_cycles"  value="busy_cycles_match_mcpat"/>

+			<!-- instruction buffer stats -->

+			<!-- ROB stats, both RS and Phy based OoOs have ROB

+			performance simulator should capture the difference on accesses,

+			otherwise, McPAT has to guess based on number of commited instructions. -->

+			<stat name="ROB_reads" value="263886"/>

+			<stat name="ROB_writes" value="263886"/>

+			<!-- RAT accesses -->

+			<stat name="rename_accesses" value="263886"/>

+			<stat name="fp_rename_accesses" value="263886"/>

+			<!-- decode and rename stage use this, should be total ic - nop -->

+			<!-- Inst window stats -->

+			<stat name="inst_window_reads" value="263886"/>

+			<stat name="inst_window_writes" value="263886"/>

+			<stat name="inst_window_wakeup_accesses" value="263886"/>

+			<stat name="fp_inst_window_reads" value="263886"/>

+			<stat name="fp_inst_window_writes" value="263886"/>

+			<stat name="fp_inst_window_wakeup_accesses" value="263886"/>

+			<!--  RF accesses -->

+			<stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>

+			<stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>

+			<stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>

+			

+			<!-- The following stat is for operand collector power - Added by Syed -->

+			<stat name="non_rf_operands" value="0"/>

+

+			<!-- accesses to the working reg -->

+			<stat name="function_calls" value="0"/>

+			<stat name="context_switches" value="0"/> <!--not used in the McPAT -->

+			<!-- Number of Windowes switches (number of function calls and returns)-->

+			<!-- Alu stats by default, the processor has one FPU that includes the divider and 

+			 multiplier. The fpu accesses should include accesses to multiplier and divider  -->

+			<stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>			

+			<stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>

+			<stat name="mul_accesses" value="mul_accesses_match_mcpat"/>

+			<stat name="cdb_alu_accesses" value="0"/>

+			<stat name="cdb_mul_accesses" value="0"/>

+			<stat name="cdb_fpu_accesses" value="0"/>

+			<!-- multiple cycle accesses should be counted multiple times, 

+			otherwise, McPAT can use internal counter for different floating point instructions 

+			to get final accesses. But that needs detailed info for floating point inst mix -->

+			<!--  currently the performance simulator should 

+			make sure all the numbers are final numbers, 

+			including the explicit read/write accesses, 

+			and the implicite accesses such as replacements and etc.

+			Future versions of McPAT may be able to reason the implicite access

+			based on param and stats of last level cache

+			The same rule applies to all cache access stats too!  -->

+			<!-- following is AF for max power computation. 

+				Do not change them, unless you understand them-->

+			<stat name="IFU_duty_cycle" value="0.25"/>			

+			<stat name="LSU_duty_cycle" value="0.25"/>

+			<stat name="MemManU_I_duty_cycle" value="1"/>

+			<stat name="MemManU_D_duty_cycle" value="0.25"/>

+			<stat name="ALU_duty_cycle" value="0.9"/>

+			<stat name="MUL_duty_cycle" value="0.5"/>

+			<stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->

+			<stat name="ALU_cdb_duty_cycle" value="0.9"/>

+			<stat name="MUL_cdb_duty_cycle" value="0.5"/>

+			<stat name="FPU_cdb_duty_cycle" value="15"/>	

+			<component id="system.core0.predictor" name="PBT">

+				<!-- branch predictor; tournament predictor see Alpha implementation -->

+				<param name="local_predictor_size" value="10,3"/>

+				<param name="local_predictor_entries" value="1024"/>

+				<param name="global_predictor_entries" value="4096"/>

+				<param name="global_predictor_bits" value="2"/>

+				<param name="chooser_predictor_entries" value="4096"/>

+				<param name="chooser_predictor_bits" value="2"/>

+				<!-- These parameters can be combined like below in next version

+				<param name="load_predictor" value="10,3,1024"/>

+				<param name="global_predictor" value="4096,2"/>

+				<param name="predictor_chooser" value="4096,2"/>

+				-->

+			</component>

+			<component id="system.core0.itlb" name="itlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+				<!-- there is no write requests to itlb although writes happen to itlb after miss, 

+				which is actually a replacement -->

+			</component>

+			<component id="system.core0.icache" name="icache">

+				<!-- there is no write requests to itlb although writes happen to it after miss, 

+				which is actually a replacement -->

+				<param name="icache_config" value="16384,128,4,1,1,3,8,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->

+				<param name="buffer_sizes" value="16, 16, 16,0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 

+				<stat name="read_accesses" value="total_instructions_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="conflicts" value="0"/>				

+			</component>

+			<component id="system.core0.dtlb" name="dtlb">

+				<param name="number_entries" value="1"/>

+				<stat name="total_accesses" value="0"/>

+				<stat name="total_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.ccache" name="ccache">

+			        <!-- all the buffer related are optional -->

+				<param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="ccache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.tcache" name="tcache">

+			        <!-- all the buffer related are optional -->

+				<param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="tcache_read_misses_match_mcpat"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+      <!--model the shared memory by mimicing dcache-->

+			<component id="system.core0.sharedmemory" name="sharedmemory">

+			        <!-- all the buffer related are optional -->

+				<param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.dcache" name="dcache">

+			        <!-- all the buffer related are optional -->

+				<param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 0"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="dcache_read_access_match_mcpat"/>

+				<stat name="write_accesses" value="dcache_write_access_match_mcpat"/>

+				<stat name="read_misses" value="dcache_read_miss_match_mcpat"/>

+				<stat name="write_misses" value="dcache_write_miss_match_mcpat"/>

+				<stat name="conflicts" value="0"/>	

+			</component>

+			<component id="system.core0.BTB" name="BTB">

+			        <!-- all the buffer related are optional -->

+				<param name="BTB_config" value="8192,4,2,1, 1,3"/>

+				<!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			</component>

+	</component>

+		<component id="system.L1Directory0" name="L1Directory0">

+				<param name="Directory_type" value="0"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="800000"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="20"/>	

+				<stat name="duty_cycle" value="0.45"/>	

+		</component>

+		<component id="system.L2Directory0" name="L2Directory0">

+				<param name="Directory_type" value="1"/>

+			    <!--0 cam based shadowed tag. 1 directory cache -->	

+				<param name="Dir_config" value="1048576,16,16,1,2, 100"/>

+				<!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->

+			    <param name="buffer_sizes" value="8, 8, 8, 8"/>	

+				<!-- all the buffer related are optional -->

+			    <param name="clockrate" value="1400"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw search ports -->

+				<param name="device_type" value="0"/>

+				<!-- altough there are multiple access types, 

+				Performance simulator needs to cast them into reads or writes

+				e.g. the invalidates can be considered as writes -->

+				<stat name="read_accesses" value="0"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>

+			    <stat name="duty_cycle" value="0.45"/>		

+		</component>

+		<component id="system.L20" name="L20">

+			<!-- all the buffer related are optional -->

+				<param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>

+			    <!-- consider 4-way bank interleaving for Niagara 1 -->

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<param name="clockrate" value="2962"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<stat name="read_accesses" value="200000"/>

+				<stat name="write_accesses" value="0"/>

+				<stat name="read_misses" value="0"/>

+				<stat name="write_misses" value="0"/>

+				<stat name="conflicts" value="0"/>	

+			    <stat name="duty_cycle" value="0.5"/>	

+		</component>

+		

+<!--**********************************************************************-->

+<component id="system.L30" name="L30">

+				<param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>

+				<!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->

+				<param name="clockrate" value="3500"/>

+				<param name="ports" value="1,1,1"/>

+				<!-- number of r, w, and rw ports -->

+				<param name="device_type" value="0"/>

+				<param name="buffer_sizes" value="16, 16, 16, 16"/>

+				<!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->	

+				<stat name="read_accesses" value="58824"/>

+				<stat name="write_accesses" value="27276"/>

+				<stat name="read_misses" value="1632"/>

+				<stat name="write_misses" value="183"/>

+				<stat name="conflicts" value="0"/>	

+	            <stat name="duty_cycle" value="0.35"/>	

+		</component>

+

+

+<!--**********************************************************************-->

+		<component id="system.NoC0" name="noc0">

+			<param name="clockrate" value="700"/>

+			<param name="type" value="1"/>

+			<!-- 1 NoC, O bus -->

+			<param name="horizontal_nodes" value="2"/>

+			<param name="vertical_nodes" value="1"/>

+			<param name="has_global_link" value="0"/>

+			<!-- 1 has global link, 0 does not have global link -->

+			<param name="link_throughput" value="1"/><!--w.r.t clock -->

+			<param name="link_latency" value="1"/><!--w.r.t clock -->

+			<!-- througput >= latency -->

+			<!-- Router architecture -->

+			<param name="input_ports" value="6"/>

+			<param name="output_ports" value="6"/>

+			<param name="virtual_channel_per_port" value="1"/>

+			<!-- input buffer; in classic routers only input ports need buffers -->

+			<param name="flit_bits" value="32"/>

+			<param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->

+			<param name="chip_coverage" value="1"/>

+			<!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->

+			<stat name="total_accesses" value="0"/>

+			<!-- This is the number of total accesses within the whole network not for each router -->

+			<stat name="duty_cycle" value="0.6"/>

+		</component>	

+<!--**********************************************************************-->

+<!--**********************************************************************-->

+

+		<component id="system.mem" name="mem">

+			<!-- Main memory property -->

+			<param name="mem_tech_node" value="23"/>

+			<param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->

+			<param name="peak_transfer_rate" value="3200"/><!--MB/S-->

+			<param name="internal_prefetch_of_DRAM_chip" value="4"/>

+			<!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->

+			<!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->

+			<!-- above numbers can be easily found from Wikipedia -->

+			<param name="capacity_per_channel" value="4096"/> <!-- MB -->

+			<!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank

+			Current McPAT assumes single DIMMs are used.--> 		

+			<param name="number_ranks" value="2"/>

+			<param name="num_banks_of_DRAM_chip" value="6"/>			

+			<param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->

+			<param name="output_width_of_DRAM_chip" value="8"/>

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->

+			<param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->

+			<param name="burstlength_of_DRAM_chip" value="8"/>

+			<stat name="memory_accesses" value="1052"/>

+			<stat name="memory_reads" value="1052"/>

+			<stat name="memory_writes" value="1052"/>									

+		</component>

+		<component id="system.mc" name="mc">

+			<!-- Memeory controllers are for DDR(2,3...) DIMMs -->

+			<!-- current version of McPAT uses published values for base parameters of memory controller

+			improvments on MC will be added in later versions. -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> 

+			<param name="peak_transfer_rate" value="29568"/><!--MB/S  Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->

+			<param name="block_size" value="64"/><!--B-->

+			<param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers  -->

+			<!-- current McPAT only supports homogeneous memory controllers -->

+			<param name="memory_channels_per_mc" value="2"/>

+			<param name="number_ranks" value="1"/>

+			<param name="withPHY" value="0"/>

+			<!-- # of ranks of each channel-->

+			<param name="req_window_size_per_channel" value="16"/>

+			<param name="IO_buffer_size_per_channel" value="16"/>

+			<param name="databus_width" value="32"/>

+			<param name="addressbus_width" value="32"/>

+			<param name="PRT_entries" value="32"/>

+			<!-- # of empirical DRAM model parameter -->

+			<param name="dram_cmd_coeff" value="0"/>

+			<param name="dram_act_coeff" value="0"/>

+			<param name="dram_nop_coeff" value="0"/>

+			<param name="dram_activity_coeff" value="0"/>

+			<param name="dram_pre_coeff" value="3.8475e-8f"/>

+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>

+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>

+			<param name="dram_req_coeff" value="0"/>

+			<param name="dram_const_coeff" value="0"/>

+

+			<!-- McPAT will add the control bus width to the addressbus width automatically -->

+			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>

+			<stat name="memory_reads" value="memory_reads_match_mcpat"/>

+			<stat name="memory_writes" value="memory_writes_match_mcpat"/>

+			<!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 

+			the average power per MC or per channel. This is sufficent for most application. 

+			Further trackdown can be easily added in later versions. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.niu" name="niu">

+			<!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller  -->

+			<!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 

+				 the low bound of clock rate of a 10Gb MAC is 150Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 

+			the average power per nic or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.pcie" name="pcie">

+			<!-- On chip PCIe controller, including Phy-->

+			<!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 

+				 the low bound of clock rate of a PCIe per lane logic is 120Mhz -->

+			<param name="type" value="0"/> <!-- 1: low power; 0 high performance -->

+			<param name="withPHY" value="1"/>

+			<param name="clockrate" value="350"/>

+			<param name="number_units" value="0"/>

+			<param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 

+			the average power per pcie controller or per channel. This is sufficent for most application. -->  			

+		</component>

+<!--**********************************************************************-->

+		<component id="system.flashc" name="flashc">

+		    <param name="number_flashcs" value="0"/>

+			<param name="type" value="1"/> <!-- 1: low power; 0 high performance -->

+            <param name="withPHY" value="1"/>

+			<param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->

+			<stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->

+			<stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth  -->

+			<!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 

+			the average power per fc or per channel. This is sufficent for most application -->  			

+		</component>

+<!--**********************************************************************-->

+

+		</component>

+</component>
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_GV100/config_volta_islip.icnt b/configs/tested-cfgs/SM7_GV100/config_volta_islip.icnt
new file mode 100644
index 0000000..5ad7ecd
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/config_volta_islip.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 144;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM7_GV100/gpgpusim.config b/configs/tested-cfgs/SM7_GV100/gpgpusim.config
new file mode 100644
index 0000000..1595c69
--- /dev/null
+++ b/configs/tested-cfgs/SM7_GV100/gpgpusim.config
@@ -0,0 +1,237 @@
+# Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas
+# Northwestern University, Purdue University, The University of British Columbia
+# All rights reserved.
+
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+
+# 1. Redistributions of source code must retain the above copyright notice, this
+#    list of conditions and the following disclaimer;
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+#    this list of conditions and the following disclaimer in the documentation
+#    and/or other materials provided with the distribution;
+# 3. Neither the names of Northwestern University, Purdue University,
+#    The University of British Columbia nor the names of their contributors
+#    may be used to endorse or promote products derived from this software
+#    without specific prior written permission.
+
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+
+# This config models the Volta Quadro V100
+# For more info about volta architecture:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70 
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+-gpgpu_kernel_launch_latency 5000
+-gpgpu_TB_launch_latency 0
+-gpgpu_max_concurrent_kernel 128
+
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
+# PTX execution-driven
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 80
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 32
+-gpgpu_n_sub_partition_per_mchannel 2 
+-gpgpu_clock_gated_lanes 1
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+-gpgpu_clock_domains 1447.0:1447.0:1447.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_registers_per_block 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+-ptx_opcode_latency_int 4,13,4,5,145,21
+-ptx_opcode_initiation_int 2,2,2,2,8,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# Volta has sub core model, in which each scheduler has its own register file and EUs
+# i.e. schedulers are isolated
+-gpgpu_sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-gpgpu_enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 70
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler lrr
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+## L1/shared memory configuration
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-gpgpu_adaptive_cache_config 1
+-gpgpu_shmem_option 0,8,16,32,64,96
+-gpgpu_unified_l1d_size 128
+# L1 cache configuration
+-gpgpu_l1_banks 4
+-gpgpu_cache:dl1  S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
+-gpgpu_l1_cache_write_ratio 25
+-gpgpu_l1_latency 20
+-gpgpu_gmem_skip_L1D 0
+-gpgpu_flush_l1_cache 1
+-gpgpu_n_cluster_ejection_buffer_size 32
+# shared memory configuration
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_sizeDefault 98304
+-gpgpu_shmem_per_block 65536
+-gpgpu_smem_latency 20
+
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-gpgpu_perf_sim_memcpy 1
+-gpgpu_memory_partition_indexing 2
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+-gpgpu_inst_fetch_throughput 4
+# 128 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+-gpgpu_perfect_inst_const_cache 1
+
+# interconnection
+#-network_mode 1 
+#-inter_config_file config_volta_islip.icnt
+# use built-in local xbar
+-network_mode 2
+-icnt_in_buffer_limit 512
+-icnt_out_buffer_limit 512
+-icnt_subnets 2
+-icnt_flit_size 40
+-icnt_arbiter_algo 1
+
+# memory partition latency config 
+-gpgpu_l2_rop_latency 160
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 850 MHZ, V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
+
+# HBM has dual bus interface, in which it can issue two col and row commands at a time
+-dram_dual_bus_interface 1
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-dram_seperate_write_queue_enable 1
+#-dram_write_queue_size 64:56:32
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
\ No newline at end of file
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 8d2b101..b3384af 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -69,7 +69,7 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
--gpgpu_clock_domains 1447.0:1447.0:1447.0:850.0
+-gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0
 # boost mode
 # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0
 
@@ -137,7 +137,7 @@
 -gpgpu_dual_issue_diff_exec_units 1
 
 ## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Defualt config is 32KB DL1 and 96KB shared memory
 # In Volta, we assign the remaining shared memory to L1 cache 
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index af561de..c37aaf0 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -107,7 +107,7 @@
 -gpgpu_dual_issue_diff_exec_units 1
 
 ## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Defualt config is 32KB DL1 and 96KB shared memory
 # In Volta, we assign the remaining shared memory to L1 cache 
diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
index aee0130..d26b1a6 100644
--- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
+++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
@@ -83,7 +83,7 @@
 -gpgpu_dual_issue_diff_exec_units 1
 
 ## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # In adaptive cache, we adaptively assign the remaining shared memory to L1 cache 
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
diff --git a/cuobjdump_to_ptxplus/cuobjdumpInstList.cc b/cuobjdump_to_ptxplus/cuobjdumpInstList.cc
index 32834c7..d42e59e 100644
--- a/cuobjdump_to_ptxplus/cuobjdumpInstList.cc
+++ b/cuobjdump_to_ptxplus/cuobjdumpInstList.cc
@@ -505,7 +505,7 @@ std::string cuobjdumpInstList::parseCuobjdumpRegister(std::string reg, bool lo,
 	} else {
 		output("ERROR: unknown register type.\n");
 		printf("\nERROR: unknown register type: ");
-		printf(reg.c_str());
+		printf("%s",reg.c_str());
 		printf("\n");
 		assert(0);
 	}
diff --git a/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus.cc b/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus.cc
index 82dcb7c..5c6fdcd 100644
--- a/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus.cc
+++ b/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus.cc
@@ -54,7 +54,7 @@ FILE *ptxplus_out;
 void output(const char * text)
 {
 	//printf(text);
-	fprintf(ptxplus_out, text);
+	fprintf(ptxplus_out,"%s", text);
 }
 
 void output(const std::string text) {
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index fd05f55..12d3aac 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -435,7 +435,7 @@ std::string get_app_binary() {
 
 // above func gives abs path whereas this give just the name of application.
 char *get_app_binary_name(std::string abs_path) {
-  char *self_exe_path;
+  char *self_exe_path = NULL;
 #ifdef __APPLE__
   // TODO: get apple device and check the result.
   printf("WARNING: not tested for Apple-mac devices \n");
@@ -463,7 +463,7 @@ static int get_app_cuda_version() {
       "ldd " + get_app_binary() +
       " | grep libcudart.so | sed  's/.*libcudart.so.\\(.*\\) =>.*/\\1/' > " +
       fname;
-  system(app_cuda_version_command.c_str());
+  int res = system(app_cuda_version_command.c_str());
   FILE *cmd = fopen(fname, "r");
   char buf[256];
   while (fgets(buf, sizeof(buf), cmd) != 0) {
@@ -1410,7 +1410,7 @@ cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlagsInternal(
   function_info *entry = context->get_kernel(hostFunc);
   printf(
       "Calculate Maxium Active Block with function ptr=%p, blockSize=%d, "
-      "SMemSize=%d\n",
+      "SMemSize=%lu\n",
       hostFunc, blockSize, dynamicSMemSize);
   if (flags == cudaOccupancyDefault) {
     // create kernel_info based on entry
@@ -3234,7 +3234,7 @@ char *readfile(const std::string filename) {
   fseek(fp, 0, SEEK_SET);
   // allocate and copy the entire ptx
   char *ret = (char *)malloc((filesize + 1) * sizeof(char));
-  fread(ret, 1, filesize, fp);
+  int num = fread(ret, 1, filesize, fp);
   ret[filesize] = '\0';
   fclose(fp);
   return ret;
@@ -3478,7 +3478,7 @@ void gpgpu_context::cuobjdumpParseBinary(unsigned int handle) {
     context->add_binary(symtab, handle);
     return;
   }
-  symbol_table *symtab;
+  symbol_table *symtab = NULL;
 
 #if (CUDART_VERSION >= 6000)
   // loops through all ptx files from smallest sm version to largest
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index fda84e8..ed7347d 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -75,7 +75,7 @@ void checkpoint::load_global_mem(class memory_space *temp_mem, char *f1name) {
   FILE *fp2 = fopen(f1name, "r");
   assert(fp2 != NULL);
   char line[128]; /* or other suitable maximum line size */
-  unsigned int offset;
+  unsigned int offset = 0;
   while (fgets(line, sizeof line, fp2) != NULL) /* read a line */
   {
     unsigned int index;
@@ -1006,13 +1006,13 @@ void simt_stack::print(FILE *fout) const {
     }
     for (unsigned j = 0; j < m_warp_size; j++)
       fprintf(fout, "%c", (stack_entry.m_active_mask.test(j) ? '1' : '0'));
-    fprintf(fout, " pc: 0x%03x", stack_entry.m_pc);
+    fprintf(fout, " pc: 0x%03llx", stack_entry.m_pc);
     if (stack_entry.m_recvg_pc == (unsigned)-1) {
       fprintf(fout, " rp: ---- tp: %s cd: %2u ",
               (stack_entry.m_type == STACK_ENTRY_TYPE_CALL ? "C" : "N"),
               stack_entry.m_calldepth);
     } else {
-      fprintf(fout, " rp: %4u tp: %s cd: %2u ", stack_entry.m_recvg_pc,
+      fprintf(fout, " rp: %4llu tp: %s cd: %2u ", stack_entry.m_recvg_pc,
               (stack_entry.m_type == STACK_ENTRY_TYPE_CALL ? "C" : "N"),
               stack_entry.m_calldepth);
     }
@@ -1032,7 +1032,7 @@ void simt_stack::print_checkpoint(FILE *fout) const {
 
     for (unsigned j = 0; j < m_warp_size; j++)
       fprintf(fout, "%c ", (stack_entry.m_active_mask.test(j) ? '1' : '0'));
-    fprintf(fout, "%d %d %d %lld %d ", stack_entry.m_pc,
+    fprintf(fout, "%llu %d %llu %lld %d ", stack_entry.m_pc,
             stack_entry.m_calldepth, stack_entry.m_recvg_pc,
             stack_entry.m_branch_div_cycle, stack_entry.m_type);
     fprintf(fout, "%d %d\n", m_warp_id, m_warp_size);
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 6e4a87d..3b95829 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -963,7 +963,7 @@ class inst_t {
   }
   bool valid() const { return m_decoded; }
   virtual void print_insn(FILE *fp) const {
-    fprintf(fp, " [inst @ pc=0x%04x] ", pc);
+    fprintf(fp, " [inst @ pc=0x%04llx] ", pc);
   }
   bool is_load() const {
     return (op == LOAD_OP || op == TENSOR_CORE_LOAD_OP ||
@@ -1157,7 +1157,7 @@ class warp_inst_t : public inst_t {
 
   // accessors
   virtual void print_insn(FILE *fp) const {
-    fprintf(fp, " [inst @ pc=0x%04x] ", pc);
+    fprintf(fp, " [inst @ pc=0x%04llx] ", pc);
     for (int i = (int)m_config->warp_size - 1; i >= 0; i--)
       fprintf(fp, "%c", ((m_warp_active_mask[i]) ? '1' : '0'));
   }
@@ -1386,7 +1386,7 @@ class register_set {
     assert(has_ready());
     warp_inst_t **ready;
     ready = NULL;
-    unsigned reg_id;
+    unsigned reg_id = 0;
     for (unsigned i = 0; i < regs.size(); i++) {
       if (not regs[i]->empty()) {
         if (ready and (*ready)->get_uid() < regs[i]->get_uid()) {
diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile
index 85d1c8c..01bc480 100644
--- a/src/cuda-sim/Makefile
+++ b/src/cuda-sim/Makefile
@@ -129,9 +129,9 @@ $(OUTPUT_DIR)/instructions.h: instructions.cc
 
 $(OUTPUT_DIR)/ptx_parser_decode.def: $(OUTPUT_DIR)/ptx.tab.c
 ifeq ($(shell uname),Linux)
-	cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed 's/^[ ]\+//' | sed 's/[=,]//g' | sed 's/\([_A-Z1-9]\+\)[ ]\+\([0-9]\+\)/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' > $(OUTPUT_DIR)/ptx_parser_decode.def
+	cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed 's/^[ ]\+//' | sed -E 's/\s+\/\*.+\*\///' | sed 's/[=,]//g' | sed 's/\([_A-Z1-9]\+\)[ ]\+\([0-9]\+\)/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' | sed '/YYerror/d;/YYEOF/d;/YYEMPTY/d;/YYUNDEF/d;'> $(OUTPUT_DIR)/ptx_parser_decode.def
 else
-	cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed -E 's/^ +//' | sed 's/[=,]//g' | sed -E 's/([_A-Z1-9]+).*/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' > $(OUTPUT_DIR)/ptx_parser_decode.def
+	cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed -E 's/^ +//' | sed -E 's/\s+\/\*.+\*\///' | sed 's/[=,]//g' | sed -E 's/([_A-Z1-9]+).*/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' | sed '/YYerror/d;/YYEOF/d;/YYEMPTY/d;/YYUNDEF/d;' > $(OUTPUT_DIR)/ptx_parser_decode.def
 endif
 
 $(OUTPUT_DIR)/instructions.o: $(OUTPUT_DIR)/instructions.h $(OUTPUT_DIR)/ptx.tab.c
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 680ce79..b063512 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -545,7 +545,7 @@ void gpgpu_t::gpu_memset(size_t dst_start_addr, int c, size_t count) {
 void cuda_sim::ptx_print_insn(address_type pc, FILE *fp) {
   std::map<unsigned, function_info *>::iterator f = g_pc_to_finfo.find(pc);
   if (f == g_pc_to_finfo.end()) {
-    fprintf(fp, "<no instruction at address 0x%x>", pc);
+    fprintf(fp, "<no instruction at address 0x%llx>", pc);
     return;
   }
   function_info *finfo = f->second;
@@ -559,7 +559,7 @@ std::string cuda_sim::ptx_get_insn_str(address_type pc) {
 #define STR_SIZE 255
     char buff[STR_SIZE];
     buff[STR_SIZE - 1] = '\0';
-    snprintf(buff, STR_SIZE, "<no instruction at address 0x%x>", pc);
+    snprintf(buff, STR_SIZE, "<no instruction at address 0x%llx>", pc);
     return std::string(buff);
   }
   function_info *finfo = f->second;
@@ -1372,7 +1372,7 @@ void function_info::add_param_data(unsigned argn,
       unsigned num_bits = 8 * args->m_nbytes;
       printf(
           "GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from "
-          "0x%x to 0x%x (shared memory space)\n",
+          "0x%llx to 0x%llx (shared memory space)\n",
           p->name().c_str(), m_symtab->get_shared_next(),
           m_symtab->get_shared_next() + num_bits / 8);
       fflush(stdout);
@@ -1503,7 +1503,7 @@ void function_info::list_param(FILE *fout) const {
     std::string name = p.get_name();
     symbol *param = m_symtab->lookup(name.c_str());
     addr_t param_addr = param->get_address();
-    fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr);
+    fprintf(fout, "%s: %#08llx\n", name.c_str(), param_addr);
   }
   fflush(fout);
 }
@@ -1533,7 +1533,11 @@ void function_info::ptx_jit_config(
            filename_c.c_str());
   assert(system(buff) != NULL);
   FILE *fp = fopen(filename_c.c_str(), "r");
-  fgets(buff, 1024, fp);
+  char * ptr = fgets(buff, 1024, fp);
+  if(ptr == NULL ){
+          printf("can't read file %s \n", filename_c.c_str());
+          assert(0);
+  }
   fclose(fp);
   std::string fn(buff);
   size_t pos1, pos2;
@@ -1877,7 +1881,7 @@ void ptx_thread_info::ptx_exec_inst(warp_inst_t &inst, unsigned lane_id) {
       dim3 tid = get_tid();
       printf(
           "%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u "
-          "[pc=%u] (%s:%u - %s)  [0x%llx]\n",
+          "[pc=%llu] (%s:%u - %s)  [0x%llx]\n",
           m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn, get_uid(), pI->uid(),
           ctaid.x, ctaid.y, ctaid.z, tid.x, tid.y, tid.z, get_icount(), pc,
           pI->source_file(), pI->source_line(), pI->get_source(),
@@ -2376,7 +2380,7 @@ void cuda_sim::read_sim_environment_variables() {
         "%s\n",
         dbg_pc);
     fflush(stdout);
-    sscanf(dbg_pc, "%d", &g_debug_pc);
+    sscanf(dbg_pc, "%llu", &g_debug_pc);
   }
 
 #if CUDART_VERSION > 1010
diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc
index 4a99c1c..8ed90bc 100644
--- a/src/cuda-sim/cuda_device_runtime.cc
+++ b/src/cuda-sim/cuda_device_runtime.cc
@@ -36,7 +36,7 @@ void cuda_device_runtime::gpgpusim_cuda_getParameterBufferV2(
   unsigned n_args = target_func->num_args();
   assert(n_args == 4);
 
-  function_info *child_kernel_entry;
+  function_info *child_kernel_entry = NULL;
   struct dim3 grid_dim, block_dim;
   unsigned int shared_mem;
 
@@ -258,7 +258,7 @@ void cuda_device_runtime::gpgpusim_cuda_streamCreateWithFlags(
   assert(n_args == 2);
 
   size_t generic_pStream_addr;
-  addr_t pStream_addr;
+  addr_t pStream_addr = 0;
   unsigned int flags;
   for (unsigned arg = 0; arg < n_args; arg++) {
     const operand_info &actual_param_op =
diff --git a/src/cuda-sim/memory.cc b/src/cuda-sim/memory.cc
index 1323837..036bada 100644
--- a/src/cuda-sim/memory.cc
+++ b/src/cuda-sim/memory.cc
@@ -109,11 +109,11 @@ void memory_space_impl<BSIZE>::read_single_block(mem_addr_t blk_idx,
   if ((addr + length) > (blk_idx + 1) * BSIZE) {
     printf(
         "GPGPU-Sim PTX: ERROR * access to memory \'%s\' is unaligned : "
-        "addr=0x%x, length=%zu\n",
+        "addr=0x%llx, length=%zu\n",
         m_name.c_str(), addr, length);
     printf(
-        "GPGPU-Sim PTX: (addr+length)=0x%lx > 0x%x=(index+1)*BSIZE, "
-        "index=0x%x, BSIZE=0x%x\n",
+        "GPGPU-Sim PTX: (addr+length)=0x%llx > 0x%llx=(index+1)*BSIZE, "
+        "index=0x%llx, BSIZE=0x%x\n",
         (addr + length), (blk_idx + 1) * BSIZE, blk_idx, BSIZE);
     throw 1;
   }
@@ -169,7 +169,7 @@ void memory_space_impl<BSIZE>::print(const char *format, FILE *fout) const {
   typename map_t::const_iterator i_page;
 
   for (i_page = m_data.begin(); i_page != m_data.end(); ++i_page) {
-    fprintf(fout, "%s %08x:", m_name.c_str(), i_page->first);
+    fprintf(fout, "%s %08llx:", m_name.c_str(), i_page->first);
     i_page->second.print(format, fout);
   }
 }
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 029cf73..f25f1d5 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1470,7 +1470,7 @@ std::string ptx_instruction::to_string() const {
   unsigned used_bytes = 0;
   if (!is_label()) {
     used_bytes +=
-        snprintf(buf + used_bytes, STR_SIZE - used_bytes, " PC=0x%03x ", m_PC);
+        snprintf(buf + used_bytes, STR_SIZE - used_bytes, " PC=0x%03llx ", m_PC);
   } else {
     used_bytes +=
         snprintf(buf + used_bytes, STR_SIZE - used_bytes, "                ");
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 4e91763..df35498 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -95,7 +95,7 @@ void gpgpu_context::print_ptx_file(const char *p, unsigned source_num,
     const ptx_instruction *pI = ptx_parser->ptx_instruction_lookup(filename, n);
     char pc[64];
     if (pI && pI->get_PC())
-      snprintf(pc, 64, "%4u", pI->get_PC());
+      snprintf(pc, 64, "%4llu", pI->get_PC());
     else
       snprintf(pc, 64, "    ");
     printf("    _%u.ptx  %4u (pc=%s):  %s\n", source_num, n, pc, t);
@@ -240,7 +240,7 @@ void fix_duplicate_errors(char fname2[1024]) {
   unsigned oldlinenum = 1;
   unsigned linenum;
   char *startptr = ptxdata;
-  char *funcptr;
+  char *funcptr = NULL;
   char *tempptr = ptxdata - 1;
   char *lineptr = ptxdata - 1;
 
@@ -320,7 +320,7 @@ void fix_duplicate_errors(char fname2[1024]) {
 // we need the application name here too.
 char *get_app_binary_name() {
   char exe_path[1025];
-  char *self_exe_path;
+  char *self_exe_path = NULL;
 #ifdef __APPLE__
   // AMRUTH:  get apple device and check the result.
   printf("WARNING: not tested for Apple-mac devices \n");
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 86a33c2..a80eeae 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -206,7 +206,7 @@ void ptx_recognizer::end_function() {
   gpgpu_ptx_assemble(g_func_info->get_name(), g_func_info);
   g_current_symbol_table = g_global_symbol_table;
 
-  PTX_PARSE_DPRINTF("function %s, PC = %d\n", g_func_info->get_name().c_str(),
+  PTX_PARSE_DPRINTF("function %s, PC = %llu\n", g_func_info->get_name().c_str(),
                     g_func_info->get_start_PC());
 }
 
@@ -486,7 +486,7 @@ void ptx_recognizer::add_identifier(const char *identifier, int array_dim,
     case param_space_local:
       printf(
           "GPGPU-Sim PTX: allocating stack frame region for .param \"%s\" from "
-          "0x%x to 0x%lx\n",
+          "0x%llx to 0x%llx\n",
           identifier, g_current_symbol_table->get_local_next(),
           g_current_symbol_table->get_local_next() + num_bits / 8);
       fflush(stdout);
@@ -521,7 +521,7 @@ void ptx_recognizer::add_constptr(const char *identifier1,
 
   unsigned addr = s2->get_address();
 
-  printf("GPGPU-Sim PTX: moving \"%s\" from 0x%x to 0x%x (%s+%x)\n",
+  printf("GPGPU-Sim PTX: moving \"%s\" from 0x%llx to 0x%x (%s+%d)\n",
          identifier1, s1->get_address(), addr + offset, identifier2, offset);
 
   s1->set_address(addr + offset);
diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc
index dc801f8..6503499 100644
--- a/src/cuda-sim/ptx_sim.cc
+++ b/src/cuda-sim/ptx_sim.cc
@@ -369,7 +369,7 @@ static void print_reg(FILE *fp, std::string name, ptx_reg_t value,
       fprintf(fp, ".u64 %llu [0x%llx]\n", value.u64, value.u64);
       break;
     case F16_TYPE:
-      fprintf(fp, ".f16 %f [0x%04x]\n", value.f16, (unsigned)value.u16);
+      fprintf(fp, ".f16 %f [0x%04x]\n", static_cast<float>(value.f16), (unsigned)value.u16);
       break;
     case F32_TYPE:
       fprintf(fp, ".f32 %.15lf [0x%08x]\n", value.f32, value.u32);
diff --git a/src/debug.cc b/src/debug.cc
index 29506bd..e23ffd4 100644
--- a/src/debug.cc
+++ b/src/debug.cc
@@ -124,7 +124,7 @@ void gpgpu_sim::gpgpu_debug() {
     fflush(stdout);
 
     char line[1024];
-    fgets(line, 1024, stdin);
+    char * ptr = fgets(line, 1024, stdin);
 
     char *tok = strtok(line, " \t\n");
     if (!strcmp(tok, "dp")) {
@@ -136,7 +136,11 @@ void gpgpu_sim::gpgpu_debug() {
       fflush(stdout);
     } else if (!strcmp(tok, "q") || !strcmp(tok, "quit")) {
       printf("\nreally quit GPGPU-Sim (y/n)?\n");
-      fgets(line, 1024, stdin);
+      ptr = fgets(line, 1024, stdin);
+      if(ptr == NULL ){
+        printf("can't read input\n");
+        exit(0);
+      }
       tok = strtok(line, " \t\n");
       if (!strcmp(tok, "y")) {
         exit(0);
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 19714ec..f4f83f9 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -519,7 +519,7 @@ void linear_to_raw_address_translation::sweep_test() const {
           h->second, raw_addr);
       abort();
     } else {
-      assert((int)tlx.chip < m_n_channel);
+      assert(tlx.chip < m_n_channel);
       // ensure that partition_address() returns the concatenated address
       if ((ADDR_CHIP_S != -1 and raw_addr >= (1ULL << ADDR_CHIP_S)) or
           (ADDR_CHIP_S == -1 and raw_addr >= (1ULL << addrdec_mklow[CHIP]))) {
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4bbf7e2..aa693b5 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -563,10 +563,12 @@ class cache_config {
     char ct, rp, wp, ap, mshr_type, wap, sif;
 
     int ntok =
-        sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", &ct,
-               &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap, &sif,
-               &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
-               &m_miss_queue_size, &m_result_fifo_entries, &m_data_port_width);
+        sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", 
+            &ct, &m_nset, &m_line_sz, &m_assoc, 
+            &rp, &wp, &ap, &wap, &sif,
+            &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
+            &m_miss_queue_size, &m_result_fifo_entries, 
+            &m_data_port_width);
 
     if (ntok < 12) {
       if (!strcmp(config, "none")) {
@@ -721,9 +723,17 @@ class cache_config {
           "Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ "
           "cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
     }
+
     if (m_cache_type == SECTOR) {
-      assert(m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
-             m_line_sz % SECTOR_SIZE == 0);
+      bool cond = 
+            m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
+            m_line_sz % SECTOR_SIZE == 0;
+      if(!cond){
+          std::cerr<<"error: For sector cache, the simulator uses hard-coded "
+             "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size "
+             "must be product of both values.\n";
+          assert(0);
+        }
     }
 
     // default: port to data array width and granularity = line size
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 5af244b..ea50fa0 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -586,26 +586,26 @@ void shader_core_config::reg_options(class OptionParser *opp) {
       "ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_"
       "INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
       "1,1,1,1,1,1,1,1,1,1,1,1,1");
-  option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_UINT32,
                          &gpgpu_tensor_core_avail,
                          "Tensor Core Available (default=0)", "0");
-  option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_num_sp_units", OPT_UINT32,
                          &gpgpu_num_sp_units, "Number of SP units (default=1)",
                          "1");
-  option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_num_dp_units", OPT_UINT32,
                          &gpgpu_num_dp_units, "Number of DP units (default=0)",
                          "0");
-  option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_num_int_units", OPT_UINT32,
                          &gpgpu_num_int_units,
                          "Number of INT units (default=0)", "0");
-  option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_UINT32,
                          &gpgpu_num_sfu_units, "Number of SF units (default=1)",
                          "1");
-  option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32,
+  option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_UINT32,
                          &gpgpu_num_tensor_core_units,
                          "Number of tensor_core units (default=1)", "0");
   option_parser_register(
-      opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
+      opp, "-gpgpu_num_mem_units", OPT_UINT32, &gpgpu_num_mem_units,
       "Number if ldst units (default=1) WARNING: not hooked up to anything",
       "1");
   option_parser_register(
@@ -2053,7 +2053,7 @@ void gpgpu_sim::cycle() {
           m_cluster[i]->get_current_occupancy(active, total);
         }
         DPRINTFG(LIVENESS,
-                 "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f\% [%llu / %llu]) "
+                 "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f%% [%llu / %llu]) "
                  "sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s",
                  gpu_tot_sim_insn + gpu_sim_insn,
                  (double)gpu_sim_insn / (double)gpu_sim_cycle,
diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc
index 0e20462..df6bd7b 100644
--- a/src/gpgpu-sim/local_interconnect.cc
+++ b/src/gpgpu-sim/local_interconnect.cc
@@ -159,8 +159,8 @@ void xbar_router::RR_Advance() {
   }
 
   if (verbose) {
-    printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
-    printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+    printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+    printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
   }
 
   // collect some stats about buffer util
@@ -217,7 +217,7 @@ void xbar_router::iSLIP_Advance() {
             out_buffers[_packet.output_deviceID].push(_packet);
             in_buffers[node_id].pop();
             if (verbose)
-              printf("%d : cycle %d : send req from %d to %d\n", m_id, cycles,
+              printf("%d : cycle %llu : send req from %d to %d\n", m_id, cycles,
                      node_id, i - _n_shader);
             if (grant_cycles_count == 1)
               next_node[i] = (++node_id % total_nodes);
@@ -228,7 +228,7 @@ void xbar_router::iSLIP_Advance() {
                   Packet _packet2 = in_buffers[node_id2].front();
 
                   if (_packet2.output_deviceID == i)
-                    printf("%d : cycle %d : cannot send req from %d to %d\n",
+                    printf("%d : cycle %llu : cannot send req from %d to %d\n",
                            m_id, cycles, node_id2, i - _n_shader);
                 }
               }
@@ -248,7 +248,7 @@ void xbar_router::iSLIP_Advance() {
   }
 
   if (verbose)
-    printf("%d : cycle %d : grant_cycles = %d\n", m_id, cycles, grant_cycles);
+    printf("%d : cycle %llu : grant_cycles = %d\n", m_id, cycles, grant_cycles);
 
   if (active && grant_cycles_count == 1)
     grant_cycles_count = grant_cycles;
@@ -256,8 +256,8 @@ void xbar_router::iSLIP_Advance() {
     grant_cycles_count--;
 
   if (verbose) {
-    printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
-    printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+    printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+    printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
   }
 
   // collect some stats about buffer util
diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc
index 470f2f9..45a09bc 100644
--- a/src/gpgpu-sim/power_interface.cc
+++ b/src/gpgpu-sim/power_interface.cc
@@ -269,7 +269,7 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
   if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WM]))
     l1_write_misses = power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel;
 
-    if(aggregate_power_stats){
+  if(aggregate_power_stats){
       power_stats->tot_inst_execution += power_stats->get_total_inst(1);
       power_stats->tot_int_inst_execution +=  power_stats->get_total_int_inst(1);
       power_stats->tot_fp_inst_execution +=  power_stats->get_total_fp_inst(1);
@@ -281,16 +281,16 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
         l1_read_hits + l1_read_misses,
         l1_write_hits + l1_write_misses,
         power_stats->commited_inst_execution);
-    }
-    else{
-    wrapper->set_inst_power(
+  }
+  else{
+        wrapper->set_inst_power(
         shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this
         cycle, power_stats->get_total_inst(1),
         power_stats->get_total_int_inst(1), power_stats->get_total_fp_inst(1),
         l1_read_hits + l1_read_misses,
         l1_write_hits + l1_write_misses,
         power_stats->get_committed_inst(1));
-    }
+  }
 
     // Single RF for both int and fp ops -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register files
     wrapper->set_regfile_power(power_stats->get_regfile_reads(1),
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index a9732d8..69992f7 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() {
     m_pipeline_reg.push_back(
         register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
   }
-  for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+  for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
     m_pipeline_reg.push_back(
         register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
                      m_config->m_specialized_unit[j].name));
@@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() {
     m_specilized_dispatch_reg.push_back(
         &m_pipeline_reg[m_pipeline_reg.size() - 1]);
   }
-  for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+  for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
     m_pipeline_reg.push_back(
         register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
                      m_config->m_specialized_unit[j].name));
@@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() {
     if (m_config->gpgpu_num_int_units > 0)
       assert(m_config->gpgpu_num_sched_per_core ==
              m_pipeline_reg[ID_OC_INT].get_size());
-    for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+    for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
       if (m_config->m_specialized_unit[j].num_units > 0)
         assert(m_config->gpgpu_num_sched_per_core ==
                m_config->m_specialized_unit[j].id_oc_spec_reg_width);
@@ -1645,7 +1645,7 @@ void swl_scheduler::order_warps() {
 }
 
 void shader_core_ctx::read_operands() {
-  for (int i = 0; i < m_config->reg_file_port_throughput; ++i)
+  for (unsigned int i = 0; i < m_config->reg_file_port_throughput; ++i)
     m_operand_collector.step();
 }
 
@@ -1949,7 +1949,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
   if (inst.accessq_empty()) return result;
 
   if (m_config->m_L1D_config.l1_latency > 0) {
-    for (int j = 0; j < m_config->m_L1D_config.l1_banks;
+    for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks;
          j++) {  // We can handle at max l1_banks reqs per cycle
 
       if (inst.accessq_empty()) return result;
@@ -2003,7 +2003,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
 }
 
 void ldst_unit::L1_latency_queue_cycle() {
-  for (int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
+  for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
     if ((l1_latency_queue[j][0]) != NULL) {
       mem_fetch *mf_next = l1_latency_queue[j][0];
       std::list<cache_event> events;
@@ -2330,7 +2330,7 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config,
 
 specialized_unit::specialized_unit(register_set *result_port,
                                    const shader_core_config *config,
-                                   shader_core_ctx *core, unsigned supported_op,
+                                   shader_core_ctx *core, int supported_op,
                                    char *unit_name, unsigned latency,
                                    unsigned issue_reg_id)
     : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) {
@@ -3084,7 +3084,7 @@ void warp_inst_t::print(FILE *fout) const {
     fprintf(fout, "bubble\n");
     return;
   } else
-    fprintf(fout, "0x%04x ", pc);
+    fprintf(fout, "0x%04llx ", pc);
   fprintf(fout, "w%02d[", m_warp_id);
   for (unsigned j = 0; j < m_config->warp_size; j++)
     fprintf(fout, "%c", (active(j) ? '1' : '0'));
@@ -3270,7 +3270,7 @@ void shader_core_ctx::display_pipeline(FILE *fout, int print_mem,
   if (!m_inst_fetch_buffer.m_valid)
     fprintf(fout, "bubble\n");
   else {
-    fprintf(fout, "w%2u : pc = 0x%x, nbytes = %u\n",
+    fprintf(fout, "w%2u : pc = 0x%llx, nbytes = %u\n",
             m_inst_fetch_buffer.m_warp_id, m_inst_fetch_buffer.m_pc,
             m_inst_fetch_buffer.m_nbytes);
   }
@@ -3503,7 +3503,7 @@ void shader_core_ctx::cycle() {
   execute();
   read_operands();
   issue();
-  for (int i = 0; i < m_config->inst_fetch_throughput; ++i) {
+  for (unsigned int i = 0; i < m_config->inst_fetch_throughput; ++i) {
     decode();
     fetch();
   }
@@ -3936,7 +3936,7 @@ bool shd_warp_t::waiting() {
 
 void shd_warp_t::print(FILE *fout) const {
   if (!done_exit()) {
-    fprintf(fout, "w%02u npc: 0x%04x, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
+    fprintf(fout, "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
             m_warp_id, m_next_pc, (functional_done() ? 'f' : ' '),
             (stores_done() ? 's' : ' '), (inst_in_pipeline() ? ' ' : 'i'),
             (done_exit() ? 'e' : ' '), n_completed, m_inst_in_pipeline,
@@ -4012,7 +4012,7 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) {
 
   sub_core_model = shader->get_config()->sub_core_model;
   m_num_warp_scheds = shader->get_config()->gpgpu_num_sched_per_core;
-  unsigned reg_id;
+  unsigned reg_id = 0;
   if (sub_core_model) {
     assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0);
     assert(m_num_warp_scheds <= m_cu.size() &&
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 986105e..9243077 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1284,7 +1284,7 @@ class sp_unit : public pipelined_simd_unit {
 class specialized_unit : public pipelined_simd_unit {
  public:
   specialized_unit(register_set *result_port, const shader_core_config *config,
-                   shader_core_ctx *core, unsigned supported_op,
+                   shader_core_ctx *core, int supported_op,
                    char *unit_name, unsigned latency, unsigned issue_reg_id);
   virtual bool can_issue(const warp_inst_t &inst) const {
     if (inst.op != m_supported_op) {
@@ -1297,7 +1297,7 @@ class specialized_unit : public pipelined_simd_unit {
   bool is_issue_partitioned() { return true; }
 
  private:
-  unsigned m_supported_op;
+  int m_supported_op;
 };
 
 class simt_core_cluster;
@@ -1622,13 +1622,13 @@ class shader_core_config : public core_config {
   unsigned int gpgpu_operand_collector_num_out_ports_gen;
   unsigned int gpgpu_operand_collector_num_out_ports_int;
 
-  int gpgpu_num_sp_units;
-  int gpgpu_tensor_core_avail;
-  int gpgpu_num_dp_units;
-  int gpgpu_num_sfu_units;
-  int gpgpu_num_tensor_core_units;
-  int gpgpu_num_mem_units;
-  int gpgpu_num_int_units;
+  unsigned int gpgpu_num_sp_units;
+  unsigned int gpgpu_tensor_core_avail;
+  unsigned int gpgpu_num_dp_units;
+  unsigned int gpgpu_num_sfu_units;
+  unsigned int gpgpu_num_tensor_core_units;
+  unsigned int gpgpu_num_mem_units;
+  unsigned int gpgpu_num_int_units;
 
   // Shader core resources
   unsigned gpgpu_shader_registers;
diff --git a/src/gpgpu-sim/stat-tool.cc b/src/gpgpu-sim/stat-tool.cc
index 0513d17..08bbe9e 100644
--- a/src/gpgpu-sim/stat-tool.cc
+++ b/src/gpgpu-sim/stat-tool.cc
@@ -519,7 +519,7 @@ void thread_insn_span::print_span(FILE *fout) const {
   fprintf(fout, "%d: ", (int)m_cycle);
   span_count_map::const_iterator i_sc = m_insn_span_count.begin();
   for (; i_sc != m_insn_span_count.end(); ++i_sc) {
-    fprintf(fout, "%d ", i_sc->first);
+    fprintf(fout, "%llx ", i_sc->first);
   }
   fprintf(fout, "\n");
 }
diff --git a/src/intersim2/networks/anynet.cpp b/src/intersim2/networks/anynet.cpp
index 4db1dfb..d7c6f22 100644
--- a/src/intersim2/networks/anynet.cpp
+++ b/src/intersim2/networks/anynet.cpp
@@ -491,7 +491,7 @@ void AnyNet::readFile(){
   }
   sort(node_check.begin(), node_check.end());
   for(size_t i = 0; i<node_check.size(); i++){
-    if(node_check[i] != i){
+    if(node_check[i] != (int)i){
       cout<<"Anynet:booksim trafficmanager assumes sequential node numbering starting at 0\n";
       assert(false);
     }
diff --git a/src/intersim2/networks/kncube.cpp b/src/intersim2/networks/kncube.cpp
index 03e13e7..178c905 100644
--- a/src/intersim2/networks/kncube.cpp
+++ b/src/intersim2/networks/kncube.cpp
@@ -231,7 +231,7 @@ void KNCube::InsertRandomFaults( const Configuration &config )
   int num_fails;
   unsigned long prev_seed;
 
-  int node, chan;
+  int node, chan = 0;
   int i, j, t, n, c;
   bool available;
 
diff --git a/src/intersim2/networks/qtree.cpp b/src/intersim2/networks/qtree.cpp
index 7214947..37d3d7c 100644
--- a/src/intersim2/networks/qtree.cpp
+++ b/src/intersim2/networks/qtree.cpp
@@ -84,7 +84,7 @@ void QTree::_BuildNet( const Configuration& config )
 {
 
   ostringstream routerName;
-  int h, r, pos, port;
+  int h, r = 0 , pos, port;
 
   for (h = 0; h < _n; h++) {
     for (pos = 0 ; pos < powi( _k, h ) ; ++pos ) {
diff --git a/src/intersim2/vc.cpp b/src/intersim2/vc.cpp
index 94e8c6b..4c94445 100644
--- a/src/intersim2/vc.cpp
+++ b/src/intersim2/vc.cpp
@@ -82,7 +82,7 @@ void VC::AddFlit( Flit *f )
   assert(f);
 
   if(_expected_pid >= 0) {
-    if(f->pid != _expected_pid) {
+    if((long long int)f->pid != _expected_pid) {
       ostringstream err;
       err << "Received flit " << f->id << " with unexpected packet ID: " << f->pid 
 	  << " (expected: " << _expected_pid << ")";
diff --git a/src/stream_manager.h b/src/stream_manager.h
index afcbb0e..561f54b 100644
--- a/src/stream_manager.h
+++ b/src/stream_manager.h
@@ -73,7 +73,7 @@ struct CUevent_st {
   int m_uid;
   bool m_blocking;
   bool m_done;
-  int m_updates;
+  unsigned int m_updates;
   unsigned int m_issued;
   time_t m_wallclock;
   double m_gpu_tot_sim_cycle;