minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED

8 files changed, 103 insertions, 48 deletions

diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config
index 2510d21..3daa539 100755
--- a/cuda-kernels/gpgpusim.config
+++ b/cuda-kernels/gpgpusim.config
@@ -33,7 +33,7 @@
 # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
 ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6
+-gpgpu_pipeline_widths 4,1,1,1,1,4,1,1,1,1,6
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 1
 # Instruction latencies and initiation intervals
diff --git a/cutlass-example/gpgpusim.config b/cutlass-example/gpgpusim.config
index 2510d21..3daa539 100644
--- a/cutlass-example/gpgpusim.config
+++ b/cutlass-example/gpgpusim.config
@@ -33,7 +33,7 @@
 # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
 ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6
+-gpgpu_pipeline_widths 4,1,1,1,1,4,1,1,1,1,6
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 1
 # Instruction latencies and initiation intervals
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index d668de7..b24a77e 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -184,7 +184,7 @@ void warp_inst_t::generate_mem_accesses()
 {
     if( empty() || op == MEMORY_BARRIER_OP || m_mem_accesses_created ) 
         return;
-    if ( !((op == LOAD_OP) || (op == STORE_OP)) )
+    if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op==VP_LOAD_OP)  || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP)||(op==VP_STORE_OP)))
         return; 
     if( m_warp_active_mask.count() == 0 ) 
         return; // predicated off
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 781509f..9c418fa 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -81,6 +81,10 @@ enum uarch_op_t {
    VP_CORE_OP,
    ALU_SFU_OP,
    LOAD_OP,
+   VP_LOAD_OP,
+   TENSOR_CORE_LOAD_OP,
+   TENSOR_CORE_STORE_OP,
+   VP_STORE_OP,
    STORE_OP,
    BRANCH_OP,
    BARRIER_OP,
@@ -801,8 +805,8 @@ public:
     {
         fprintf(fp," [inst @ pc=0x%04x] ", pc );
     }
-    bool is_load() const { return (op == LOAD_OP || memory_op == memory_load); }
-    bool is_store() const { return (op == STORE_OP || memory_op == memory_store); }
+    bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP||op==VP_LOAD_OP || memory_op == memory_load); }
+    bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP||op==VP_STORE_OP || memory_op == memory_store); }
     unsigned get_num_operands() const {return num_operands;}
     unsigned get_num_regs() const {return num_regs;}
     void set_num_regs(unsigned num) {num_regs=num;}
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index bcf64c4..8f684e2 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -648,12 +648,12 @@ void ptx_instruction::set_opcode_and_latency()
        if ( has_memory_write() ) op = STORE_OP;
        break;
    case LD_OP: op = LOAD_OP; break;
-   case MMA_LD_OP: op = LOAD_OP; break;
-   case VP_LD_OP: op = LOAD_OP; break;
+   case MMA_LD_OP: op = TENSOR_CORE_LOAD_OP; break;
+   case VP_LD_OP: op = VP_LOAD_OP; break;
    case LDU_OP: op = LOAD_OP; break;
    case ST_OP: op = STORE_OP; break;
-   case MMA_ST_OP: op = STORE_OP; break;
-   case VP_ST_OP: op = STORE_OP; break;
+   case MMA_ST_OP: op = TENSOR_CORE_STORE_OP; break;
+   case VP_ST_OP: op = VP_STORE_OP; break;
    case BRA_OP: op = BRANCH_OP; break;
    case BREAKADDR_OP: op = BRANCH_OP; break;
    case TEX_OP: op = LOAD_OP; mem_op=TEX; break;
@@ -1334,6 +1334,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
             skip = !pred_lookup(pI->get_pred_mod(), pred_value.pred & 0x000F);
       }
    }
+   int inst_opcode=pI->get_opcode();
    
    if( skip ) {
       inst.set_not_active(lane_id);
@@ -1346,17 +1347,21 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          pI = pJ;
       }
      
-      int inst_opcode=pI->get_opcode();
+      if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))){
+      		if(inst.active_count()!=MAX_WARP_SIZE)
+			while(1); 
+      }
 
       if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP)&&(inst_opcode!=VP_LD_OP)&&(inst_opcode!=VP_ST_OP)&&(inst_opcode!=VP_MMA_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)&&(lane_id==0))){
-      switch ( inst_opcode ) {
-#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
-#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
-#include "opcodes.def"
-#undef OP_DEF
-#undef OP_W_DEF
-      default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break;
-      }}
+	      switch ( inst_opcode ) {
+	#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
+	#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
+	#include "opcodes.def"
+	#undef OP_DEF
+	#undef OP_W_DEF
+	      default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break;
+	      }
+      }
       delete pJ;
       pI = pI_saved;
       
@@ -1398,13 +1403,17 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
    _memory_op_t insn_memory_op = no_memory_op;
    unsigned insn_data_size = 0;
    if ( (pI->has_memory_read()  || pI->has_memory_write()) ) {
-      insn_memaddr = last_eaddr();
-      insn_space = last_space();
-      unsigned to_type = pI->get_type();
-      insn_data_size = datatype2size(to_type);
-      insn_memory_op = pI->has_memory_read() ? memory_load : memory_store;
+      //if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)))
+      //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP)))
+      //{
+        insn_memaddr = last_eaddr();
+        insn_space = last_space();
+        unsigned to_type = pI->get_type();
+        insn_data_size = datatype2size(to_type);
+        insn_memory_op = pI->has_memory_read() ? memory_load : memory_store;
+      //}	
    }
-
+  
    if ( pI->get_opcode() == BAR_OP && pI->barrier_op() == RED_OPTION) {
 	   inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,false /*not atomic*/);
    }
@@ -1476,12 +1485,16 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
    
    // "Return values"
    if(!skip) {
-      inst.space = insn_space;
-      inst.set_addr(lane_id, insn_memaddr);
-      inst.data_size = insn_data_size; // simpleAtomicIntrinsics
-      assert( inst.memory_op == insn_memory_op );
-   } 
-
+      //if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)))
+      //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP)))
+      //{
+   	  inst.space = insn_space;
+          inst.set_addr(lane_id, insn_memaddr);
+          inst.data_size = insn_data_size; // simpleAtomicIntrinsics
+          assert( inst.memory_op == insn_memory_op );
+      //} 
+   }
+ 
    } catch ( int x  ) {
       printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() );
       printf("GPGPU-Sim PTX:       '%s'\n", pI->get_source() );
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 39b8ba5..77e8e71 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -3196,6 +3196,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
    unsigned wmma_type = pI->get_wmma_type();
    unsigned wmma_layout = pI->get_wmma_layout(0);
    int stride; 
+   _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store;
    for (thrd=0; thrd < core->get_warp_size(); thrd++) {
 	thread = core->get_thread_info()[tid+thrd];
 	odd=thrd%2;
@@ -3224,6 +3225,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
    	if(g_debug_instruction)
 		printf("mma_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32);
 	addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;  
+	addr_t push_addr;
 
 	ptx_reg_t nw_v[8];
 	for(k=0;k<8;k++){
@@ -3235,7 +3237,10 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 
 	for(k=0;k<8;k++){
 		if(type==F32_TYPE){
-       			mem->write(new_addr+4*acc_float_offset(k,wmma_layout,stride),size/8,&v[k].s64,thread,pI);
+       			//mem->write(new_addr+4*acc_float_offset(k,wmma_layout,stride),size/8,&v[k].s64,thread,pI);
+       			push_addr=new_addr+4*acc_float_offset(k,wmma_layout,stride);
+       			mem->write(push_addr,size/8,&v[k].s64,thread,pI);
+
 			if(g_debug_instruction){
 				printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,v[0].s64,v[1].s64,v[2].s64,v[3].s64,v[4].s64,v[5].s64,v[6].s64,v[7].s64);   
 				float temp;
@@ -3250,10 +3255,16 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	
 		}
 		else if(type==F16_TYPE){
-			if(wmma_layout==ROW)
-       				mem->write(new_addr+k*2,size/8,&nw_v[k].s64,thread,pI);
-			else if(wmma_layout==COL)
-       				mem->write(new_addr+k*2*stride,size/8,&nw_v[k].s64,thread,pI);
+			if(wmma_layout==ROW){
+       				//mem->write(new_addr+k*2,size/8,&nw_v[k].s64,thread,pI);
+       				push_addr=new_addr+k*2;
+       				mem->write(push_addr,size/8,&nw_v[k].s64,thread,pI);
+			}
+			else if(wmma_layout==COL){
+       				//mem->write(new_addr+k*2*stride,size/8,&nw_v[k].s64,thread,pI);
+       				push_addr=new_addr+k*2*stride;
+       				mem->write(push_addr,size/8,&nw_v[k].s64,thread,pI);
+			}
 			if(g_debug_instruction)
 				printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,nw_v[0].s64,nw_v[1].s64,nw_v[2].s64,nw_v[3].s64,nw_v[4].s64,nw_v[5].s64,nw_v[6].s64,nw_v[7].s64);   
 		}
@@ -3427,6 +3438,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
    int tid = inst.warp_id_func()*core->get_warp_size();
    int thrd,stride;
    ptx_thread_info *thread;
+   _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store;
    
    for (thrd=0; thrd < core->get_warp_size(); thrd++){
    	thread = core->get_thread_info()[tid+thrd];
@@ -3452,13 +3464,18 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 		printf("mma_ld: thrd=%d,addr=%x, fpsize=%d, stride=%d\n",thrd,src1_data.u32,size,src2_data.u32);
 	
 	addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;  
-
+	addr_t fetch_addr;
 	if(wmma_type==LOAD_A){
 		for(i=0;i<16;i++){
-			if(wmma_layout==ROW)
-				mem->read(new_addr+2*i,size/8,&data[i].s64);
+			if(wmma_layout==ROW){
+				//mem->read(new_addr+2*i,size/8,&data[i].s64);
+				fetch_addr=new_addr+2*i;
+				mem->read(fetch_addr,size/8,&data[i].s64);
+			}
 			else if(wmma_layout==COL){
-				mem->read(new_addr+2*(i%4)+2*stride*4*(i/4),size/8,&data[i].s64);
+				//mem->read(new_addr+2*(i%4)+2*stride*4*(i/4),size/8,&data[i].s64);
+				fetch_addr=new_addr+2*(i%4)+2*stride*4*(i/4);
+				mem->read(fetch_addr,size/8,&data[i].s64);
 			}
 			else{
 				printf("mma_ld:wrong_layout_type\n");
@@ -3468,10 +3485,15 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	}
 	else if(wmma_type==LOAD_B){
 		for(i=0;i<16;i++){
-			if(wmma_layout==COL)
-				mem->read(new_addr+2*i,size/8,&data[i].s64);
+			if(wmma_layout==COL){
+				//mem->read(new_addr+2*i,size/8,&data[i].s64);
+				fetch_addr=new_addr+2*i;
+				mem->read(fetch_addr,size/8,&data[i].s64);
+			}
 			else if(wmma_layout==ROW){
-				mem->read(new_addr+2*(i%4)+2*stride*4*(i/4),size/8,&data[i].s64);
+				//mem->read(new_addr+2*(i%4)+2*stride*4*(i/4),size/8,&data[i].s64);
+				fetch_addr=new_addr+2*(i%4)+2*stride*4*(i/4);
+				mem->read(fetch_addr,size/8,&data[i].s64);
 			}
 			else{
 				printf("mma_ld:wrong_layout_type\n");
@@ -3482,17 +3504,25 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
 	else if(wmma_type==LOAD_C){
 		for(i=0;i<8;i++){
 			if(type==F16_TYPE){
-				if(wmma_layout==ROW)
-					mem->read(new_addr+2*i,size/8,&data[i].s64);
-				else if(wmma_layout==COL)
-					mem->read(new_addr+2*stride*i,size/8,&data[i].s64);
+				if(wmma_layout==ROW){
+					//mem->read(new_addr+2*i,size/8,&data[i].s64);
+					fetch_addr=new_addr+2*i;
+					mem->read(fetch_addr,size/8,&data[i].s64);
+				}
+				else if(wmma_layout==COL){
+					//mem->read(new_addr+2*stride*i,size/8,&data[i].s64);
+					fetch_addr=new_addr+2*stride*i;
+					mem->read(fetch_addr,size/8,&data[i].s64);
+				}
 				else{
 					printf("mma_ld:wrong_type\n");
 					abort();
 				}
 			}
 			else if(type==F32_TYPE){
-				mem->read(new_addr+4*acc_float_offset(i,wmma_layout,stride),size/8,&data[i].s64);
+				//mem->read(new_addr+4*acc_float_offset(i,wmma_layout,stride),size/8,&data[i].s64);
+				fetch_addr=new_addr+4*acc_float_offset(i,wmma_layout,stride);
+				mem->read(fetch_addr,size/8,&data[i].s64);
 			}
 			else{
 				printf("wrong type");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 6f11ad9..5e80fb1 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -920,7 +920,7 @@ void scheduler_unit::cycle()
                         ready_inst = true;
                         const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
                         assert( warp(warp_id).inst_in_pipeline() );
-                        if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
+                        if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
                             if( m_mem_out->has_free() ) {
                                 m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
                                 issued++;
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index d292d56..d9558b0 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1116,7 +1116,11 @@ public:
         switch(inst.op) {
         case SFU_OP: return false; 
         case LOAD_OP: return false;
+        case TENSOR_CORE_LOAD_OP: return false;
+        case VP_LOAD_OP: return false;
         case STORE_OP: return false;
+        case TENSOR_CORE_STORE_OP: return false;
+        case VP_STORE_OP: return false;
         case MEMORY_BARRIER_OP: return false;
         default: break;
         }
@@ -1158,7 +1162,11 @@ public:
     {
         switch(inst.op) {
         case LOAD_OP: break;
+        case TENSOR_CORE_LOAD_OP: break;
+        case VP_LOAD_OP: break;
         case STORE_OP: break;
+        case TENSOR_CORE_STORE_OP: break;
+        case VP_STORE_OP: break;
         case MEMORY_BARRIER_OP: break;
         default: return false;
         }