Fixed address operands of PTX memory instructions being ignored in predecode. See Bug 138

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11573]

2 files changed, 31 insertions, 16 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 21c3b4a..e8611fb 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -632,23 +632,35 @@ void ptx_instruction::pre_decode()
    // Assuming only one memory operand per instruction,
    //  and maximum of two address registers for one memory operand.
    if( has_memory_read() || has_memory_write() ) {
-	  ptx_instruction::const_iterator op=op_iter_begin();
-	  for ( ; op != op_iter_end(); op++, n++ ) { //process operands
-	     const operand_info &o = *op;
+      ptx_instruction::const_iterator op=op_iter_begin();
+      for ( ; op != op_iter_end(); op++, n++ ) { //process operands
+         const operand_info &o = *op;
 
-	     // memory operand with addressing (ex. s[0x4] or g[$r1])
-	     if(o.is_memory_operand2()) {
-	    	 // memory operand with one address register (ex. g[$r1] or s[$r2+0x4])
-	    	 if(o.get_double_operand_type() == 0 && o.is_memory_operand()){
-				 ar1 = o.reg_num();
-	    	 }
-	    	 // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2])
-	    	 else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) {
-	    		 ar1 = o.reg1_num();
-	    		 ar2 = o.reg2_num();
-	    	 }
-	     }
-	  }
+         if(o.is_memory_operand()) {
+
+            // Check PTXPlus-type operand
+            // memory operand with addressing (ex. s[0x4] or g[$r1])
+            if(o.is_memory_operand2()) {
+
+               // memory operand with one address register (ex. g[$r1+0x4] or s[$r2+=0x4])
+               if(o.get_double_operand_type() == 0 || o.get_double_operand_type() == 3){
+                  ar1 = o.reg_num();
+                  // TODO: address register in $r2+=0x4 should be an output register as well
+               }
+               // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2])
+               else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) {
+                  ar1 = o.reg1_num();
+                  ar2 = o.reg2_num();
+                  // TODO: first address register in $r1+=$r2 should be an output register as well
+               }
+            }
+            // Regular PTX operand
+            else if (o.get_symbol()->type()->get_key().is_reg()) { // Memory operand contains a register
+              ar1 = o.reg_num();
+            }
+
+         }
+      }
    }
 
    // get reconvergence pc
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index c7eb499..1c945d7 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -601,6 +601,7 @@ public:
    bool is_memory_operand() const { return m_type == memory_t;}
 
    // Memory operand with immediate access (ex. s[0x0004] or g[$r1+=0x0004])
+   // This is used by the PTXPlus extension. The operand is assigned an address space during parsing.
    bool is_memory_operand2() const { 
       return (m_addr_space!=undefined_space); 
    }
@@ -907,6 +908,7 @@ public:
    bool has_memory_read() const {
       if( m_opcode == LD_OP || m_opcode == TEX_OP ) 
          return true;
+      // Check PTXPlus operand type below
       // Source operands are memory operands
       ptx_instruction::const_iterator op=op_iter_begin();
       for ( int n=0; op != op_iter_end(); op++, n++ ) { //process operands
@@ -917,6 +919,7 @@ public:
    }
    bool has_memory_write() const {
       if( m_opcode == ST_OP ) return true;
+      // Check PTXPlus operand type below
       // Destination operand is a memory operand
       ptx_instruction::const_iterator op=op_iter_begin();
       for ( int n=0; (op!=op_iter_end() && n<1); op++, n++ ) { //process operands