Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types for specific caches.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]

3 files changed, 30 insertions, 18 deletions

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 8e2e759..a5b82ee 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -547,16 +547,17 @@ typedef std::bitset<MAX_MEMORY_ACCESS_SIZE> mem_access_byte_mask_t;
 #define MEM_ACCESS_TYPE_TUP_DEF \
 MA_TUP_BEGIN( mem_access_type ) \
    MA_TUP( GLOBAL_ACC_R ), \
-   MA_TUP( LOCAL_ACC_R), \
-   MA_TUP( CONST_ACC_R), \
-   MA_TUP( TEXTURE_ACC_R), \
-   MA_TUP( GLOBAL_ACC_W), \
-   MA_TUP( LOCAL_ACC_W), \
-   MA_TUP( L1_WRBK_ACC), \
-   MA_TUP( L2_WRBK_ACC), \
-   MA_TUP( INST_ACC_R), \
-   MA_TUP( L2_WR_ALLOC_R), \
-   MA_TUP( NUM_MEM_ACCESS_TYPE) \
+   MA_TUP( LOCAL_ACC_R ), \
+   MA_TUP( CONST_ACC_R ), \
+   MA_TUP( TEXTURE_ACC_R ), \
+   MA_TUP( GLOBAL_ACC_W ), \
+   MA_TUP( LOCAL_ACC_W ), \
+   MA_TUP( L1_WRBK_ACC ), \
+   MA_TUP( L2_WRBK_ACC ), \
+   MA_TUP( INST_ACC_R ), \
+   MA_TUP( L1_WR_ALLOC_R ), \
+   MA_TUP( L2_WR_ALLOC_R ), \
+   MA_TUP( NUM_MEM_ACCESS_TYPE ) \
 MA_TUP_END( mem_access_type ) 
 
 #define MA_TUP_BEGIN(X) enum X {
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index f927e9a..469d6dd 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -813,7 +813,7 @@ data_cache::wr_miss_wa( new_addr_type addr,
     //if(!send_write_allocate(mf, addr, block_addr, cache_index, time, events))
     //    return RESERVATION_FAIL;
 
-    const mem_access_t *ma = new  mem_access_t( L2_WR_ALLOC_R,
+    const mem_access_t *ma = new  mem_access_t( m_wr_alloc_type,
                         mf->get_addr(),
                         mf->get_data_size(),
                         false, // Now performing a read
@@ -841,7 +841,7 @@ data_cache::wr_miss_wa( new_addr_type addr,
         // (already modified lower level)
         if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { 
             mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
-                L2_WRBK_ACC,m_config.get_line_sz(),true);
+                m_wrbk_type,m_config.get_line_sz(),true);
             m_miss_queue.push_back(wb);
             wb->set_status(m_miss_queue_status,time);
         }
@@ -923,7 +923,7 @@ data_cache::rd_miss_base( new_addr_type addr,
         // (already modified lower level)
         if(wb && (m_config.m_write_policy != WRITE_THROUGH) ){ 
             mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr,
-                L1_WRBK_ACC,m_config.get_line_sz(),true);
+                m_wrbk_type,m_config.get_line_sz(),true);
         send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events);
     }
         return MISS;
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 9a0ea4b..a775ac9 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -694,10 +694,13 @@ class data_cache : public baseline_cache {
 public:
     data_cache( const char *name, cache_config &config,
     			int core_id, int type_id, mem_fetch_interface *memport,
-                mem_fetch_allocator *mfcreator, enum mem_fetch_status status )
+                mem_fetch_allocator *mfcreator, enum mem_fetch_status status,
+                mem_access_type wr_alloc_type, mem_access_type wrbk_type )
     			: baseline_cache(name,config,core_id,type_id,memport,status)
     {
         init( mfcreator );
+        m_wr_alloc_type = wr_alloc_type;
+        m_wrbk_type = wrbk_type;
     }
 
     virtual ~data_cache() {}
@@ -751,11 +754,19 @@ protected:
                 mem_fetch_interface *memport,
                 mem_fetch_allocator *mfcreator,
                 enum mem_fetch_status status,
-                tag_array* new_tag_array )
+                tag_array* new_tag_array,
+                mem_access_type wr_alloc_type,
+                mem_access_type wrbk_type)
     : baseline_cache(name, config, core_id, type_id, memport,status, new_tag_array)
     {
         init( mfcreator );
+        m_wr_alloc_type = wr_alloc_type;
+        m_wrbk_type = wrbk_type;
     }
+
+    mem_access_type m_wr_alloc_type; // Specifies type of write allocate request (e.g., L1 or L2)
+    mem_access_type m_wrbk_type; // Specifies type of writeback request (e.g., L1 or L2)
+
     //! A general function that takes the result of a tag_array probe
     //  and performs the correspding functions based on the cache configuration
     //  The access fucntion calls this function
@@ -891,7 +902,7 @@ public:
     l1_cache(const char *name, cache_config &config,
             int core_id, int type_id, mem_fetch_interface *memport,
             mem_fetch_allocator *mfcreator, enum mem_fetch_status status )
-            : data_cache(name,config,core_id,type_id,memport,mfcreator,status){}
+            : data_cache(name,config,core_id,type_id,memport,mfcreator,status, L1_WR_ALLOC_R, L1_WRBK_ACC){}
 
     virtual ~l1_cache(){}
 
@@ -912,7 +923,7 @@ protected:
               tag_array* new_tag_array )
     : data_cache( name,
                   config,
-                  core_id,type_id,memport,mfcreator,status, new_tag_array ){}
+                  core_id,type_id,memport,mfcreator,status, new_tag_array, L1_WR_ALLOC_R, L1_WRBK_ACC ){}
 
 };
 
@@ -923,7 +934,7 @@ public:
     l2_cache(const char *name,  cache_config &config,
             int core_id, int type_id, mem_fetch_interface *memport,
             mem_fetch_allocator *mfcreator, enum mem_fetch_status status )
-            : data_cache(name,config,core_id,type_id,memport,mfcreator,status){}
+            : data_cache(name,config,core_id,type_id,memport,mfcreator,status, L2_WR_ALLOC_R, L2_WRBK_ACC){}
 
     virtual ~l2_cache() {}