diff options
| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2018-09-12 21:03:00 -0400 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-09-12 21:03:00 -0400 |
| commit | 96bbd0063b479ad51f3d296f5e87a56151536d86 (patch) | |
| tree | 320ab1c7893c0b359c78984291c17ee99d417c19 | |
| parent | bd2b9b3e64ea420917f9e85ab176ca7bbc48c1e9 (diff) | |
change L1 indexing to linear for TITANX
| -rw-r--r-- | configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 9ea7202..8b47f98 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -65,9 +65,9 @@ # Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB # Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 |