diff options
| author | Wilson Fung <[email protected]> | 2012-11-02 04:00:26 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:21 -0700 |
| commit | 9af6f86d0f06c2ca1b117d358009b91a646b0e83 (patch) | |
| tree | 10509be824e0ba4d41e826138ae7225c9c3fd43c | |
| parent | d0b377ded0c804580a78f2327b84e6e2ea1ee069 (diff) | |
Fixed the timing model for LDU instruction, before it was not recognized as a memory instruction in the timing model.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14538]
| -rw-r--r-- | CHANGES | 2 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 3 | ||||
| -rw-r--r-- | src/cuda-sim/ptx_ir.cc | 2 | ||||
| -rw-r--r-- | src/cuda-sim/ptx_ir.h | 2 |
4 files changed, 6 insertions, 3 deletions
@@ -60,6 +60,8 @@ Version 3.1.1+edits (development branch) versus 3.1.1 - Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. Added options to configure the number of shared memory banks per shader core and to allow a more flexible broadcast mechanism. + - Fixed the timing model for LDU instruction, before it was not recognized + as a memory instruction in the timing model. Version 3.1.1 versus 3.1.0 - Add checks to top level makefile to ensure setup_environment is run and checks to diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 06fb7d3..85afe73 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -495,6 +495,7 @@ void ptx_instruction::set_opcode_and_latency() if ( has_memory_write() ) op = STORE_OP; break; case LD_OP: op = LOAD_OP; break; + case LDU_OP: op = LOAD_OP; break; case ST_OP: op = STORE_OP; break; case BRA_OP: op = BRANCH_OP; break; case BREAKADDR_OP: op = BRANCH_OP; break; @@ -724,7 +725,7 @@ void ptx_instruction::pre_decode() case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; default: - if( m_opcode == LD_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP ) cache_op = CACHE_ALL; else if( m_opcode == ST_OP ) cache_op = CACHE_WRITE_BACK; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 26c9a00..29f6ff4 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1151,7 +1151,7 @@ ptx_instruction::ptx_instruction( int opcode, } m_scalar_type = scalar_type; m_space_spec = space_spec; - if( ( opcode == ST_OP || opcode == LD_OP ) && (space_spec == undefined_space) ) { + if( ( opcode == ST_OP || opcode == LD_OP || opcode == LDU_OP ) && (space_spec == undefined_space) ) { m_space_spec = generic_space; } for( std::vector<operand_info>::const_iterator i=m_operands.begin(); i!=m_operands.end(); ++i) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 09c9ade..ffd0c58 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -922,7 +922,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == TEX_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP ) return true; // Check PTXPlus operand type below // Source operands are memory operands |