diff options
| author | Wilson Fung <[email protected]> | 2012-06-28 00:01:59 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:47:33 -0700 |
| commit | d8057bf4260f596a11a61b0e0037dac5a6c5efc9 (patch) | |
| tree | 1308e61d5b25296031b99f2c6b7b7569e883aeb5 | |
| parent | 7fbcae0be90ab124192e818dd9fafbc3e9f5b0e9 (diff) | |
Updating the TeslaC2050 config to use the proper GDDR5 frequency and to support the right number of threads.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13227]
| -rw-r--r-- | configs/TeslaC2050/gpgpusim.config | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 0d9fb61..d51f0d4 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -12,13 +12,13 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 575.0:1150.0:575.0:1500.0 +-gpgpu_clock_domains 575.0:1150.0:575.0:750.0 # shader core pipeline config -gpgpu_shader_registers 32768 # This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_core_pipeline 1536:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -37,14 +37,13 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 - # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq> -gpgpu_cache:dl1 32:128:4:L:R:m,A:32:8,8 -gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6:L:R:f,A:32:8,8 +#-gpgpu_cache:dl1 64:128:6:L:R:m,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache @@ -75,6 +74,7 @@ # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 |