Move ptx_tex_regs

Signed-off-by: Mengchi Zhang <[email protected]>

2 files changed, 12 insertions, 10 deletions

diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h
index 194309a..b3b6b73 100644
--- a/src/cuda-sim/cuda-sim.h
+++ b/src/cuda-sim/cuda-sim.h
@@ -133,6 +133,7 @@ class cuda_sim {
 	    g_assemble_code_next_pc=0;
 	    g_debug_thread_uid = 0;
 	    g_override_embedded_ptx = false;
+	    ptx_tex_regs = NULL;
 	    gpgpu_ctx = ctx;
 	}
 	//global variables
@@ -169,6 +170,7 @@ class cuda_sim {
 	int g_debug_thread_uid;
 	bool g_override_embedded_ptx;
 	std::set<unsigned long long> g_ptx_cta_info_sm_idx_used;
+	ptx_reg_t* ptx_tex_regs;
 	// backward pointer
 	class gpgpu_context* gpgpu_ctx;
 	//global functions
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index a72bc0c..dfe5af6 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -5146,7 +5146,6 @@ void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not
 void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
 
-ptx_reg_t* ptx_tex_regs = NULL;
 
 union intfloat {
    int a;
@@ -5260,9 +5259,10 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    unsigned c_type = pI->get_type2();
    fflush(stdout);
    ptx_reg_t data1, data2, data3, data4;
-   if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4];
+   if (!thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs)
+       thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs = new ptx_reg_t[4];
    unsigned nelem = src2.get_vect_nelem();
-   thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture
+   thread->get_vector_operand_values(src2, thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture
    /*
      For programs with many streams, textures can be bound and unbound
      asynchronously.  This means we need to use the kernel's "snapshot" of
@@ -5299,7 +5299,7 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
       height = cuArray->height;
       if (texref->normalized) {
          assert(c_type == F32_TYPE); 
-         x_f32 = ptx_tex_regs[0].f32;
+         x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
          if (texref->addressMode[0] == cudaAddressModeClamp) {
             x_f32 = (x_f32 > 1.0)? 1.0 : x_f32;
             x_f32 = (x_f32 < 0.0)? 0.0 : x_f32;
@@ -5322,11 +5322,11 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
       } else {
          switch ( c_type ) {
          case S32_TYPE: 
-            x = ptx_tex_regs[0].s32; 
+            x = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].s32;
             assert(texref->filterMode == cudaFilterModePoint); 
             break; 
          case F32_TYPE: 
-            x_f32 = ptx_tex_regs[0].f32; 
+            x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
             alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling)
             x = (int) x_f32; 
             break; 
@@ -5349,8 +5349,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
       width = cuArray->width;
       height = cuArray->height;
       if (texref->normalized) {
-         x_f32 = reduce_precision(ptx_tex_regs[0].f32,16);
-         y_f32 = reduce_precision(ptx_tex_regs[1].f32,15);
+         x_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32,16);
+         y_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32,15);
 
          if (texref->addressMode[0]) {//clamp
             if (x_f32<0) x_f32 = 0;
@@ -5380,8 +5380,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
             y = (int) floor(y_f32 * height);
          }
       } else {
-         x_f32 = ptx_tex_regs[0].f32;
-         y_f32 = ptx_tex_regs[1].f32;
+         x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
+         y_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32;
 
          alpha = x_f32 - floor(x_f32);
          beta = y_f32 - floor(y_f32);