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| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2017-11-15 20:58:22 -0500 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2017-11-15 20:58:22 -0500 |
| commit | dccac457bb2263602a6a244297168cae8fda8e47 (patch) | |
| tree | 795ee670db8a66da8d13f3ae73e9d24ddd542602 | |
| parent | 32babbbda9c589e918ac1a2436eae0fd64c70bae (diff) | |
Update gpgpusim.config
| -rw-r--r-- | configs/Pascal-P102-GDDR5X/gpgpusim.config | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index e830023..257560e 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -22,7 +22,7 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -113,7 +113,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 0 -dram_latency 100 # dram model config @@ -123,8 +123,8 @@ # To allow 100% DRAM utility, there should at least be enough buffer to sustain # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 240 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition |