diff options
| author | Timothy G Rogers <[email protected]> | 2018-09-08 00:57:46 -0400 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-09-08 00:57:46 -0400 |
| commit | e4f8c0242f4b188638bafd4963117b751cef49f1 (patch) | |
| tree | 0aa796972c3645e35005cc31787a9b1df7fd4051 | |
| parent | 950e981534a9e0fb057b11b5ae8d86598f8953d0 (diff) | |
| parent | f4116831d7354c80dcd3cf857fcb5be7b001d70f (diff) | |
Merge branch 'dev-purdue-integration' into dev-purdue-integration
| -rw-r--r-- | src/abstract_hardware_model.h | 1 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 1 | ||||
| -rw-r--r-- | src/cuda-sim/ptx_ir.cc | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 |
4 files changed, 4 insertions, 1 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index a70b077..e708fa7 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -665,6 +665,7 @@ enum cache_operator_type { CACHE_ALL, // .ca CACHE_LAST_USE, // .lu CACHE_VOLATILE, // .cv + CACHE_L1, // .nc // loads and stores CACHE_STREAMING, // .cs diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 9246613..93bbc1d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -898,6 +898,7 @@ void ptx_instruction::pre_decode() switch( m_cache_option ) { case CA_OPTION: cache_op = CACHE_ALL; break; + case NC_OPTION: cache_op = CACHE_L1; break; case CG_OPTION: cache_op = CACHE_GLOBAL; break; case CS_OPTION: cache_op = CACHE_STREAMING; break; case LU_OPTION: cache_op = CACHE_LAST_USE; break; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index ee36957..ba6d7ed 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1211,6 +1211,7 @@ ptx_instruction::ptx_instruction( int opcode, case EXTP_OPTION: break; case NC_OPTION: + m_cache_option = last_ptx_inst_option; break; case UP_OPTION: case DOWN_OPTION: diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 51689e3..0e2e1c2 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1642,7 +1642,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea bypassL1D = true; } else if (inst.space.is_global()) { // global memory access // skip L1 cache if the option is enabled - if (m_core->get_config()->gmem_skip_L1D) + if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op)) bypassL1D = true; } |