fixing some valgrind erros by initializing uninitialized values in CACTI

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14839]

4 files changed, 160 insertions, 12 deletions

diff --git a/src/gpuwattch/cacti/cacti_interface.h b/src/gpuwattch/cacti/cacti_interface.h
index f6b6424..ff639da 100644
--- a/src/gpuwattch/cacti/cacti_interface.h
+++ b/src/gpuwattch/cacti/cacti_interface.h
@@ -110,6 +110,7 @@ enum Wire_type
 class InputParameter
 {
   public:
+	InputParameter();
     void parse_cfg(const string & infile);
 
     bool error_checking();  // return false if the input parameters are problematic
diff --git a/src/gpuwattch/cacti/io.cc b/src/gpuwattch/cacti/io.cc
index 3bcf5b8..c513dbf 100644
--- a/src/gpuwattch/cacti/io.cc
+++ b/src/gpuwattch/cacti/io.cc
@@ -797,6 +797,8 @@ uca_org_t cacti_interface(
   g_ip->nbanks              = banks;
   g_ip->out_w               = output_width;
   g_ip->specific_tag        = specific_tag;
+
+
   if (tag_width == 0) {
     g_ip->tag_w = 42;
   }
@@ -1096,7 +1098,111 @@ uca_org_t cacti_interface(
 }
 
 
+InputParameter::InputParameter()
+{
+    cache_sz=0;  // in bytes
+    line_sz=0;
+    assoc=0;
+    nbanks=0;
+    out_w=0;// == nr_bits_out
+    specific_tag=false;
+    tag_w=0;
+    access_mode=0;
+    obj_func_dyn_energy=0;
+    obj_func_dyn_power=0;
+    obj_func_leak_power=0;
+    obj_func_cycle_t=0;
+
+    F_sz_nm=0;          // feature size in nm
+    F_sz_um=0;          // feature size in um
+    num_rw_ports=0;
+    num_rd_ports=0;
+    num_wr_ports=0;
+    num_se_rd_ports=0;  // number of single ended read ports
+    num_search_ports=0;  // Sheng: number of search ports for CAM
+    is_main_mem=false;
+    is_cache=false;
+    pure_ram=false;
+    pure_cam=false;
+    rpters_in_htree=false;  // if there are repeaters in htree segment
+    ver_htree_wires_over_array=0;
+    broadcast_addr_din_over_ver_htrees=0;
+    temp=0;
+
+    ram_cell_tech_type=0;
+    peri_global_tech_type=0;
+    data_arr_ram_cell_tech_type=0;
+    data_arr_peri_global_tech_type=0;
+    tag_arr_ram_cell_tech_type=0;
+    tag_arr_peri_global_tech_type=0;
+
+    burst_len=0;
+    int_prefetch_w=0;
+    page_sz_bits=0;
+
+    ic_proj_type=0;      // interconnect_projection_type
+    wire_is_mat_type=0;  // wire_inside_mat_type
+    wire_os_mat_type=0; // wire_outside_mat_type
+    wt=Invalid_wtype;
+    force_wiretype=0;
+    print_input_args=false;
+    nuca_cache_sz=0; // TODO
+    ndbl=0;
+    ndwl=0;
+    nspd=0;
+    ndsam1=0;
+    ndsam2=0;
+    ndcm=0;
+    force_cache_config=false;
 
+    cache_level=0;
+    cores=0;
+    nuca_bank_count=0;
+    force_nuca_bank=0;
+
+    delay_wt=0;
+    dynamic_power_wt=0;
+    leakage_power_wt=0;
+    cycle_time_wt=0;
+    area_wt=0;
+    delay_wt_nuca=0;
+    dynamic_power_wt_nuca=0;
+    leakage_power_wt_nuca=0;
+    cycle_time_wt_nuca=0;
+    area_wt_nuca=0;
+
+    delay_dev=0;
+    dynamic_power_dev=0;
+    leakage_power_dev=0;
+    cycle_time_dev=0;
+    area_dev=0;
+    delay_dev_nuca=0;
+    dynamic_power_dev_nuca=0;
+    leakage_power_dev_nuca=0;
+    cycle_time_dev_nuca=0;
+    area_dev_nuca=0;
+    ed=0; //ED or ED2 optimization
+    nuca=0;
+
+    fast_access=false;
+    block_sz=0;  // bytes
+    tag_assoc=0;
+    data_assoc=0;
+    is_seq_acc=false;
+    fully_assoc=false;
+    nsets=0;  // == number_of_sets
+    print_detail=0;
+
+
+    add_ecc_b_=false;
+    //parameters for design constraint
+    throughput=0;
+    latency=0;
+    pipelinable=false;
+    pipeline_stages=0;
+    per_stage_vector=0;
+    with_clock_grid=false;
+}
 bool InputParameter::error_checking()
 {
   int  A;
diff --git a/src/gpuwattch/cacti/parameter.cc b/src/gpuwattch/cacti/parameter.cc
index b52b0f0..3f5a802 100644
--- a/src/gpuwattch/cacti/parameter.cc
+++ b/src/gpuwattch/cacti/parameter.cc
@@ -207,6 +207,21 @@ DynamicParameter::DynamicParameter(
   number_way_select_signals_mat(0), V_b_sense(0), use_inp_params(0),
   is_main_mem(is_main_mem_), cell(), is_valid(false)
 {
+
+	num_di_b_bank_per_port=0;
+	num_do_b_bank_per_port=0;
+	num_di_b_mat=0;
+	num_do_b_mat=0;
+	num_di_b_subbank=0;
+	num_do_b_subbank=0;
+	num_si_b_mat=0;
+	num_so_b_mat=0;
+	num_si_b_subbank=0;
+	num_so_b_subbank=0;
+	num_si_b_bank_per_port=0;
+	num_so_b_bank_per_port=0;
+
+
   ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type;
   is_dram            = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram));
 
@@ -214,6 +229,10 @@ DynamicParameter::DynamicParameter(
   const TechnologyParameter::InterconnectType & wire_local = g_tp.wire_local;
   fully_assoc = (g_ip->fully_assoc) ? true : false;
 
+
+
+
+
   if (fully_assoc || pure_cam)
   { // fully-assocative cache -- ref: CACTi 2.0 report
 	  if (Ndwl != 1 ||            //Ndwl is fixed to 1 for FA
diff --git a/src/gpuwattch/cacti/technology.cc b/src/gpuwattch/cacti/technology.cc
index 7cade1a..70ab6e6 100644
--- a/src/gpuwattch/cacti/technology.cc
+++ b/src/gpuwattch/cacti/technology.cc
@@ -56,13 +56,25 @@ double wire_capacitance(double wire_width, double wire_thickness, double wire_sp
 
 void init_tech_params(double technology, bool is_tag)
 {
-  int    iter, tech, tech_lo, tech_hi;
-  double curr_alpha, curr_vpp;
-  double wire_width, wire_thickness, wire_spacing,
-         fringe_cap, pmos_to_nmos_sizing_r;
+  int   iter = 0;
+  int 	tech = 0;
+  int 	tech_lo = 0;
+  int 	tech_hi = 0;
+  double curr_alpha = 0;
+  double curr_vpp = 0;
+  double wire_width = 0;
+  double wire_thickness =0;
+  double wire_spacing = 0;
+  double fringe_cap = 0;
+  double pmos_to_nmos_sizing_r = 0;
 //  double aspect_ratio,ild_thickness, miller_value = 1.5, horiz_dielectric_constant, vert_dielectric_constant;
-  double barrier_thickness, dishing_thickness, alpha_scatter;
-  double curr_vdd_dram_cell, curr_v_th_dram_access_transistor, curr_I_on_dram_cell, curr_c_dram_cell;
+  double barrier_thickness = 0;
+  double dishing_thickness = 0;
+  double alpha_scatter = 0;
+  double curr_vdd_dram_cell = 0;
+  double curr_v_th_dram_access_transistor = 0;
+  double curr_I_on_dram_cell = 0;
+  double curr_c_dram_cell = 0;
 
   uint32_t ram_cell_tech_type    = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type;
   uint32_t peri_global_tech_type = (is_tag) ? g_ip->tag_arr_peri_global_tech_type : g_ip->data_arr_peri_global_tech_type;
@@ -73,12 +85,22 @@ void init_tech_params(double technology, bool is_tag)
   g_tp.reset();
   double gmp_to_gmn_multiplier_periph_global = 0;
 
-  double curr_Wmemcella_dram, curr_Wmemcellpmos_dram, curr_Wmemcellnmos_dram,
-         curr_area_cell_dram, curr_asp_ratio_cell_dram, curr_Wmemcella_sram,
-         curr_Wmemcellpmos_sram, curr_Wmemcellnmos_sram, curr_area_cell_sram,
-         curr_asp_ratio_cell_sram, curr_I_off_dram_cell_worst_case_length_temp;
-  double curr_Wmemcella_cam, curr_Wmemcellpmos_cam, curr_Wmemcellnmos_cam, curr_area_cell_cam,//Sheng: CAM data
-         curr_asp_ratio_cell_cam;
+  double curr_Wmemcella_dram = 0;
+  double curr_Wmemcellpmos_dram = 0;
+  double curr_Wmemcellnmos_dram = 0;
+  double curr_area_cell_dram = 0;
+  double curr_asp_ratio_cell_dram = 0;
+  double curr_Wmemcella_sram = 0;
+  double curr_Wmemcellpmos_sram = 0;
+  double curr_Wmemcellnmos_sram = 0;
+  double curr_area_cell_sram = 0;
+  double curr_asp_ratio_cell_sram = 0;
+  double curr_I_off_dram_cell_worst_case_length_temp = 0;
+  double curr_Wmemcella_cam = 0;
+  double curr_Wmemcellpmos_cam = 0;
+  double curr_Wmemcellnmos_cam = 0;
+  double curr_area_cell_cam = 0;//Sheng: CAM data
+  double curr_asp_ratio_cell_cam = 0;
   double SENSE_AMP_D, SENSE_AMP_P; // J
   double area_cell_dram = 0;
   double asp_ratio_cell_dram = 0;