Fixing bug 126. Now DXTC runs to completion by not giving correct result (expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision).

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]

4 files changed, 38 insertions, 6 deletions

diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 3182a64..5f8410b 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -283,7 +283,7 @@ void function_info::create_basic_blocks()
          i = find_next_real_instruction(++i);
       } else {
          switch( pI->get_opcode() ) {
-         case BRA_OP: case RET_OP: case EXIT_OP: case RETP_OP:
+         case BRA_OP: case RET_OP: case EXIT_OP: case RETP_OP: case BREAK_OP: 
             i++;
             if( i != m_instructions.end() ) 
                leaders.push_back(*i);
@@ -389,6 +389,40 @@ void function_info::print_basic_block_links()
       printf("\n");
    }
 }
+operand_info* function_info::find_break_target( ptx_instruction * p_break_insn ) //find the target of a break instruction 
+{
+   const basic_block_t *break_bb = p_break_insn->get_bb(); 
+   // go through the dominator tree 
+   for(const basic_block_t *p_bb = break_bb; 
+       p_bb->immediatedominator_id != -1; 
+       p_bb = m_basic_blocks[p_bb->immediatedominator_id]) 
+   {
+      // reverse search through instructions in basic block for breakaddr instruction 
+      unsigned insn_addr = p_bb->ptx_end->get_m_instr_mem_index(); 
+      while (insn_addr >= p_bb->ptx_begin->get_m_instr_mem_index()) { 
+         ptx_instruction *pI = m_instr_mem[insn_addr]; 
+         insn_addr -= 1; 
+         if (pI == NULL) continue; // temporary solution for variable size instructions 
+         if (pI->get_opcode() == BREAKADDR_OP) {
+            return &(pI->dst()); 
+         }
+      }
+   }
+
+   assert(0); 
+
+   // lazy fallback: just traverse backwards? 
+   for (int insn_addr = p_break_insn->get_m_instr_mem_index(); 
+        insn_addr >= 0; insn_addr--) 
+   { 
+      ptx_instruction *pI = m_instr_mem[insn_addr]; 
+      if (pI->get_opcode() == BREAKADDR_OP) {
+         return &(pI->dst()); 
+      }
+   }
+
+   return NULL; 
+}
 void function_info::connect_basic_blocks( ) //iterate across m_basic_blocks of function, connecting basic blocks together
 {
    std::vector<basic_block_t*>::iterator bb_itr;
@@ -424,6 +458,7 @@ void function_info::connect_basic_blocks( ) //iterate across m_basic_blocks of f
          (*bb_itr)->successor_ids.insert(target_bb->bb_id);
          target_bb->predecessor_ids.insert((*bb_itr)->bb_id);
       } 
+
       if ( !(pI->get_opcode()==BRA_OP && (!pI->has_pred())) ) { 
          // if basic block does not end in an unpredicated branch, 
          // then next basic block is also successor
@@ -471,7 +506,7 @@ bool function_info::connect_break_targets() //connecting break instructions with
 
          if (pI->has_pred()) {
             // predicated break - add link to next basic block
-            unsigned next_addr = pI->get_m_instr_mem_index() + 1;
+            unsigned next_addr = pI->get_m_instr_mem_index() + pI->inst_size();
             basic_block_t *next_bb = m_instr_mem[next_addr]->get_bb();
             p_bb->successor_ids.insert(next_bb->bb_id);
             next_bb->predecessor_ids.insert(p_bb->bb_id);
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 17bd1e5..3db984d 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -767,7 +767,7 @@ void add_scalar_operand( const char *identifier )
    DPRINTF("add_scalar_operand");
    const symbol *s = g_current_symbol_table->lookup(identifier);
    if ( s == NULL ) {
-      if ( g_opcode == BRA_OP || g_opcode == CALLP_OP) {
+      if ( g_opcode == BRA_OP || g_opcode == CALLP_OP || g_opcode == BREAKADDR_OP) {
          // forward branch target...
          s = g_current_symbol_table->add_variable(identifier,NULL,0,g_filename,ptx_lineno);
       } else {
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index ddee6eb..6b448ab 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -904,8 +904,6 @@ void gpgpu_sim::cycle()
             }
             if (m_config.gpu_runtime_stat_flag & GPU_RSTAT_SHD_INFO) 
                shader_print_runtime_stat( stdout );
-            if (m_config.gpu_runtime_stat_flag & GPU_RSTAT_WARP_DIS) 
-               print_shader_cycle_distro( stdout );
             if (m_config.gpu_runtime_stat_flag & GPU_RSTAT_L1MISS) 
                shader_print_l1_miss_stat( stdout );
          }
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index ab5e8bc..7c14594 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -267,7 +267,6 @@ private:
    void shader_print_runtime_stat( FILE *fout );
    void shader_print_l1_miss_stat( FILE *fout ) const;
    void visualizer_printstat();
-   void print_shader_cycle_distro( FILE *fout ) const;
 
    void gpgpu_debug();