updating config files

6 files changed, 183 insertions, 201 deletions

diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
index 323d2d9..1951a3f 100644
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -18,12 +18,13 @@
 -gpgpu_compute_capability_major 3
 -gpgpu_compute_capability_minor 5
 
-# SASS execution (only supported with CUDA >= 4.0)
+# PTX execution-driven
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
+# SASS trace-driven mode execution
+#-trace_driven_mode 1
 
 # high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
 -gpgpu_n_clusters 14
 -gpgpu_n_cores_per_cluster 1
 -gpgpu_n_mem 12
@@ -46,15 +47,13 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Kepler has 6 SP SIMD units and 2 SFU units per SM. 
-# There is no int unit in kepler
-## we need to scale the number of pipeline registers to be equal to the number of SP units
+## Kepler has 6 SP SIMD units, 4 DPs and 2 SFU units per SM. 
+# There is no INT unit in kepler
 -gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12
 -gpgpu_num_sp_units 6
 -gpgpu_num_sfu_units 2
 -gpgpu_num_dp_units 4
 
-
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
@@ -68,6 +67,38 @@
 -ptx_opcode_initiation_sfu 2
 -ptx_opcode_latency_sfu 200
 
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use kepler Coalsce arhitetecture
+-gpgpu_coalesce_arch 35
+
+## In Kepler, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 0
+
+# Kepler TITAN has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
@@ -97,37 +128,12 @@
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 8
 # 48 KB Tex 
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
 
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use kepler Coalsce arhitetecture
--gpgpu_coalesce_arch 35
-
-## In Kepler, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 0
-
 # interconnection
 -network_mode 1 
 -inter_config_file config_kepler_islip.icnt
@@ -161,15 +167,6 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Kepler TITAN has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
 # stat collection
 -gpgpu_memlatency_stat 14 
 -gpgpu_runtime_stat 500
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index f8689c2..d54b7d4 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -13,6 +13,7 @@
 -gpgpu_heap_size_limit 8388608
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
+-gpgpu_kernel_launch_latency 5000
 
 # Compute Capability
 -gpgpu_compute_capability_major 6
@@ -23,7 +24,6 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
-# P102 has two semi-indp scheds per core, and two cores per cluster 
 -gpgpu_n_clusters 28
 -gpgpu_n_cores_per_cluster 1
 -gpgpu_n_mem 12
@@ -46,35 +46,58 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
-# There is no int unit in Pascal
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,0,4,1,4,1,0,4,1,9
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM.
+# There is no INT unit in Pascal
+-gpgpu_pipeline_widths 4,0,0,4,4,4,0,0,4,4,8
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 1
-
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_latency_int 4,13,4,4,145
 -ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_latency_fp 4,13,4,4,39
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,8,8,8,130
 -ptx_opcode_initiation_sfu 4
 -ptx_opcode_latency_sfu 8
 
+# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs
+-sub_core_model 1
+# enable operand collector 
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# 16 register banks, 4 banks per subcore
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
 
-# latencies and cache configs are adopted from:
-# https://arxiv.org/pdf/1804.06826.pdf
+## L1/shared memory configuration
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # The defulat is to disable the L1 cache, unless cache modifieres are used
+-l1_banks 2
 -gpgpu_cache:dl1  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_cache:dl1PrefL1  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_cache:dl1PrefShared  S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
@@ -92,45 +115,21 @@
 -gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2 S:1:128:1024,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 1
--memory_partition_indexing 0
+-memory_partition_indexing 4
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 8
 # 48 KB Tex 
 # Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 2
--gpgpu_operand_collector_num_out_ports_sp 2
--gpgpu_operand_collector_num_in_ports_sfu 2
--gpgpu_operand_collector_num_out_ports_sfu 2
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-# Use Pascal Coalsce arhitetecture
--gpgpu_coalesce_arch 61
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
+-perfect_inst_const_cache 1
 
 # interconnection
 -network_mode 1 
@@ -165,15 +164,6 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
 # stat collection
 -gpgpu_memlatency_stat 14 
 -gpgpu_runtime_stat 500
diff --git a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
index dec4789..eed1c34 100644
--- a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt
+++ b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt
@@ -1,4 +1,4 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
+//52*1 fly with 32 flits per packet under gpgpusim injection mode
 use_map = 0;
 flit_size = 40; 
 
diff --git a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index ab324d8..9d3992a 100644
--- a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -1,3 +1,8 @@
+# This config models the Turing RTX 2060
+# For more info about turing architecture:
+# https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf
+# "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
@@ -9,15 +14,16 @@
 -gpgpu_runtime_sync_depth_limit 2
 -gpgpu_runtime_pending_launch_count_limit 2048
 -gpgpu_kernel_launch_latency 5000
--gpgpu_TB_launch_latency 0
 
 # Compute Capability
 -gpgpu_compute_capability_major 7
--gpgpu_compute_capability_minor 0
+-gpgpu_compute_capability_minor 5
 
-# SASS execution (only supported with CUDA >= 4.0)
+# PTX execution-driven
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
+# SASS trace-driven mode execution
+#-trace_driven_mode 1
 
 # high level architecture configuration
 -gpgpu_n_clusters 30
@@ -27,8 +33,6 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Turing clock domains are adopted from 
-# https://en.wikipedia.org/wiki/GeForce_20_series
 -gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0
 # boost mode
 # -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0
@@ -36,7 +40,7 @@
 # shader core pipeline config
 -gpgpu_shader_registers 65536
 -gpgpu_registers_per_block 65536
--gpgpu_occupancy_sm_number 70
+-gpgpu_occupancy_sm_number 75
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
@@ -45,12 +49,11 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+## Turing has 4 SP SIMD units, 4 INT units, 4 SFU units, 8 Tensor core units
+## We need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,0,4,4,4,4,0,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
 -gpgpu_num_int_units 4
 -gpgpu_tensor_core_avail 1
 -gpgpu_num_tensor_core_units 4
@@ -58,8 +61,6 @@
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
 -ptx_opcode_latency_int 4,13,4,5,145
 -ptx_opcode_initiation_int 2,2,2,2,8
 -ptx_opcode_latency_fp 4,13,4,5,39
@@ -71,6 +72,34 @@
 -ptx_opcode_latency_tesnor 64
 -ptx_opcode_initiation_tensor 64
 
+# Trung has sub core model, in which each scheduler has its own register file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# turing has 8 banks dual-port, 4 schedulers, two banks per scheduler
+# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Turing, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# Turing has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 -adaptive_cache_config 0
@@ -95,6 +124,7 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 4
 # 128 KB Tex
 # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
@@ -102,30 +132,10 @@
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 -perfect_inst_const_cache 1
 
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 32
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
 # interconnection
 #-network_mode 1 
-#-inter_config_file config_volta_islip.icnt
-# for local xbar, use:
+#-inter_config_file config_turing_islip.icnt
+# use built-in local xbar
 -network_mode 2
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
@@ -141,7 +151,7 @@
 -gpgpu_frfcfs_dram_sched_queue_size 64
 -gpgpu_dram_return_queue_size 192
 
-# GDDR6
+# Turing has GDDR6
 # http://monitorinsider.com/GDDR6.html
 -gpgpu_n_mem_per_ctrlr 1
 -gpgpu_dram_buswidth 2
@@ -161,15 +171,6 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
 # stat collection
 -gpgpu_memlatency_stat 14 
 -gpgpu_runtime_stat 500
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 41aea78..1ed4fb2 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -25,7 +25,7 @@
 -gpgpu_compute_capability_major 7
 -gpgpu_compute_capability_minor 0
 
-# SASS execution (only supported with CUDA >= 4.0)
+# PTX execution-driven
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
 
@@ -37,8 +37,6 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA TITANV  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
 -gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0
 # boost mode
 # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0
@@ -68,8 +66,6 @@
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
 -ptx_opcode_latency_int 4,13,4,5,145
 -ptx_opcode_initiation_int 2,2,2,2,8
 -ptx_opcode_latency_fp 4,13,4,5,39
@@ -81,6 +77,30 @@
 -ptx_opcode_latency_tesnor 64
 -ptx_opcode_initiation_tensor 64
 
+# Volta has sub core model, in which each scheduler has its own register file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+## L1/shared memory configuration
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Defualt config is 32KB DL1 and 96KB shared memory
@@ -91,7 +111,6 @@
 -adaptive_cache_config 1
 # Volta unified cache has four banks
 -l1_banks 4
-#-mem_unit_ports 4
 -gpgpu_cache:dl1  S:1:128:256,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gpgpu_shmem_sizeDefault 98304
@@ -112,6 +131,7 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 4
 # 128 KB Tex
 # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
@@ -119,31 +139,10 @@
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 -perfect_inst_const_cache 1
 
-# Volta has sub core model, in which each scheduler has its own register file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 32
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
 # interconnection
 #-network_mode 1 
 #-inter_config_file config_volta_islip.icnt
-# for local xbar, use:
+# use built-in local xbar
 -network_mode 2
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
index ba50287..0255f76 100644
--- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
@@ -12,7 +12,6 @@
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
--trace_driven_mode 1
 
 # Device Limits
 -gpgpu_stack_size_limit 1024
@@ -25,7 +24,8 @@
 -gpgpu_compute_capability_major 7
 -gpgpu_compute_capability_minor 0
 
-# SASS execution (only supported with CUDA >= 4.0)
+# SASS trace-driven mode support
+-trace_driven_mode 1
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
 
@@ -37,8 +37,6 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA TITANV  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
 -gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0
 # boost mode
 # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0
@@ -68,8 +66,6 @@
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
 -ptx_opcode_latency_int 4,13,4,5,145
 -ptx_opcode_initiation_int 2,2,2,2,8
 -ptx_opcode_latency_fp 4,13,4,5,39
@@ -81,6 +77,35 @@
 -ptx_opcode_latency_tesnor 6
 -ptx_opcode_initiation_tensor 2
 
+# Volta has sub core model, in which each scheduler has its own register file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version
+-gpgpu_num_reg_banks 16
+-gpgpu_reg_file_port_throughput 2
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+## L1/shared memory configuration
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Defualt config is 32KB DL1 and 96KB shared memory
@@ -91,7 +116,6 @@
 -adaptive_cache_config 1
 # Volta unified cache has four banks
 -l1_banks 4
-#-mem_unit_ports 4
 -gpgpu_cache:dl1  S:1:128:256,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gpgpu_shmem_sizeDefault 98304
@@ -112,6 +136,7 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+-inst_fetch_throughput 4
 # 128 KB Tex
 # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
@@ -119,31 +144,10 @@
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 -perfect_inst_const_cache 1
 
-# Volta has sub core model, in which each scheduler has its own register file and EUs
-# i.e. schedulers are isolated
--sub_core_model 1
-# disable specialized operand collectors and use generic operand collectors instead
--enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 32
--gpgpu_operand_collector_num_in_ports_gen 8
--gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Volta, a warp scheduler can issue 1 inst per cycle
--gpgpu_max_insn_issue_per_warp 1
--gpgpu_dual_issue_diff_exec_units 1
-
 # interconnection
 #-network_mode 1 
 #-inter_config_file config_volta_islip.icnt
-# for local xbar, use:
+# use built-in local xbar
 -network_mode 2
 -inct_in_buffer_limit 512
 -inct_out_buffer_limit 512
@@ -186,15 +190,6 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Volta has four schedulers per core
--gpgpu_num_sched_per_core 4
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
 # stat collection
 -gpgpu_memlatency_stat 14 
 -gpgpu_runtime_stat 500