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authorTim Rogers <[email protected]>2018-11-20 16:13:16 -0500
committerGitHub <[email protected]>2018-11-20 16:13:16 -0500
commit6443f21d433f1b642003867e56fe1f54efae55e3 (patch)
tree6e017904f8dbeab9925810e775a3eaf874d23fdc /CHANGES
parent8ec70c69eb89c1fa836c233be3e4c478602d9bb7 (diff)
parent695592593ac59be49bdc013814710e216d18a438 (diff)
Merge pull request #83 from purdue-aalp/dev
INT unit, sub-core-model, Increase L1 throughput and add tensor core config parameters
Diffstat (limited to 'CHANGES')
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1 files changed, 2 insertions, 1 deletions
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index c5b97fc..2a4222b 100644
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@@ -14,11 +14,12 @@ Version 4.0.0 (development branch) versus 3.2.3
4- debug support for wmma instruction using debug_tensorcore flag
-GPU Core Performance Simulation:
1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors.
-2- Adding separate dp unit pipeline.
+2- Adding separate int and dp units pipeline.
3- diff dual issue: allow scheduler to issue diff insts at a time
4- Fair memory issue from multiple schedulers.
5- Added tensorcore unit pipeline.
6- Corrected the bug in vector load instruction
+7- Volta sub-core model (scheduler isolation)
-Cache System:
1- Sector L1/L2 cache
2- Fetch-on-write and lazy-fetch-on-read write allocation policy.