Lengthened the DRAM return queue size to have enough credits in order to keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]

1 files changed, 4 insertions, 1 deletions

diff --git a/CHANGES b/CHANGES
index c743ce1..0be0d4c 100644
--- a/CHANGES
+++ b/CHANGES
@@ -35,7 +35,10 @@ Version 3.2.1+edits (development branch) versus 3.2.1
 - Redesigned the memory partition microarchitecture model to allow multiple L2
   cache banks (sub partitions) in each memory partition.  Each memory partition
   contains a single DRAM scheduler, and one or more L2 cache banks.  Each L2
-  cache bank has an independent port to the interconnection network.  
+  cache bank has an independent port to the interconnection network.  The
+  configuration files are changes to have a larger DRAM return queue to allow
+  the credit-based arbiter between the sub partitions and the DRAM scheduler to
+  tolerate the minimum DRAM latency.  
 - Bug Fixes:
     - Fixed the flit count sent to GPUWattch for atomic operations. 
     - Fix for Bug 51 - Updated the function declaration of