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authorAndrew M. B. Boktor <[email protected]>2011-11-11 22:18:31 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:18:24 -0700
commitfcad95c34f96a519af8d37afe43ca8e92373d48c (patch)
tree4ca888f1a671b090cfd4f151de7a584eb15b8e0e /CHANGES
parenta2506a85e77bb9810195715b851e1ceea5acb80f (diff)
Updated CHANGES with the differences since the last release.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10900]
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CHANGE LOG:
+Version 3.1.0b versus 3.0.0b
+- Added prints for L1 data cache statistics
+- Added read-to-precharge constraint in DRAM
+- Disabled Stream Manager's verbose output by default, use debug level 3 to
+ enable it
+- Addresses returned by memory allocation are now 256 bytes aligned
+- Ejection from the clock domain interface buffer between interconnection
+ network and L2 cache happens in the L2 clock domain instead of interconnect
+ clock domain.
+- Testing the simulator on Ubuntu 10.04.3 LTS
+- Added Doxygen generated documentation
+- Bug fixes
+ - Fixed the variation in instruction count seen under different cache
+ configurations on the same workload
+ - Fixed unnecessary flushing of instruction buffer
+ - Fixed mislabeling of stall cycles recorded by scheduler
+ - Fixed compilation issues when using gcc 4.5.1
+ - Cleanup and bugfixes to build scripts
+ - Fixed gpu_sim_cycle with sequential kernel launches
Version 3.0.0b versus 2.1.2b
- massive refactoring of code to C++ (most global variables eliminated)