Refactoring:

1. Moving mem_access_t to abstract_hardware_model and making set (queue) of
   accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept
   rather than a hardware organization concept.  This is only partly "done"...
 	   logic for computing accesses is still part of shader_core_ctx in this CL.
          Given number of warp_inst_t accessors for accessq, now seems like we might even 
   want to move some memory stage code into warp_inst_t class.  How those
   accesses make it to memory system is the hardware concept.
2. Making warp_inst_t an explicit arguement of subroutines used in memory stage...
   The eventual goal here is (likely) to refactor memory into a hardware block...
   i.e., have function units be a class that contains some set of pipeline stages
   internally and some set of input/output "ports".
3. Moving accessor functions is_load, is_store; is_const, is_local into class
   declaration (where they belong).
4. Removing code for selecting pipeline uarch (might add it back later, but first
   want a clean GT200 organization). In particular, removing option to have an
   operand collector -- now you MUST have the operand collector.
5. Removing more deadcode from prior changes (fixed delay queue related)

Scripts/configs:
6. Correlation script not printing out exit condition when hardware launch fails
7. Update config files to have proper compute model selected

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]

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