diff options
| author | Mahmoud <[email protected]> | 2018-10-11 12:58:35 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-10-11 12:58:35 -0400 |
| commit | a6b9171a158d29d5d1ad415d087f483feb1af965 (patch) | |
| tree | 0c1c1d1768a05c6340153909b294a6de7b2cbc53 /configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | |
| parent | d78eab6fdc4eb9ab9e0a86088a16872c2c6f9755 (diff) | |
enable memcpu-perf by deafault
Diffstat (limited to 'configs/4.x-cfgs/SM7_TITANV/gpgpusim.config')
| -rw-r--r-- | configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config index 41757f8..6fe441b 100644 --- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config @@ -79,13 +79,12 @@ -l1_latency 28 -smem_latency 19 -gpgpu_flush_l1_cache 1 --adpative_volta_cache_config 1 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 0 +-perf_sim_memcpy 1 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 |