diff options
| author | Wilson Fung <[email protected]> | 2012-02-25 19:55:49 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:19:03 -0700 |
| commit | 9899f1418112e9e31895e4d65078d9c028e60a3c (patch) | |
| tree | b260f44b8e636f74fcdb0e626ed035f95ac91d68 /configs/Fermi | |
| parent | 955763630783eaf5eb945ecc92829d279598690d (diff) | |
Updated Fermi config: Changed the ICNT clock domain to model a faster interconnect for Fermi. Halved the dram buswidth option to properly model the peak DRAM bandwidth. Changed L2 cache line to 256B.
Also further shortened the bandwidth test to speed up measurement.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11516]
Diffstat (limited to 'configs/Fermi')
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index 6ee3e0a..e416cfb 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -1,7 +1,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 15 +-gpgpu_ptx_force_max_capability 20 # high level architecture configuration -gpgpu_n_clusters 15 @@ -12,13 +12,13 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:1848.0 +-gpgpu_clock_domains 700.0:1400.0:700.0:1848.0 # shader core pipeline config -gpgpu_shader_registers 32768 # This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32:32 +-gpgpu_shader_core_pipeline 1536:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -33,7 +33,7 @@ #-gpgpu_shmem_size 16384 # 256 sets, each 512 bits 6-way, this gives 786KB L2 cache --gpgpu_cache:dl2 256:512:6:L:R:m,A:32:4,4 +-gpgpu_cache:dl2 512:256:6:L:R:m,A:32:4,4 #-gpgpu_cache:dl2_texture_only -gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4 @@ -53,10 +53,10 @@ # dram model config -gpgpu_dram_scheduler 1 -gpgpu_dram_sched_queue_size 16 --gpgpu_n_mem_per_ctrlr 2 -# for Fermi, bus width is 384bits, this is 8 bytes per memory partition --gpgpu_dram_buswidth 8 +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 4 -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS |