Lengthened the DRAM return queue size to have enough credits in order to keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]

1 files changed, 6 insertions, 1 deletions

diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index 62dd078..a1d6517 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -85,8 +85,13 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 16
+-gpgpu_dram_return_queue_size 116
 
 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
 -gpgpu_n_mem_per_ctrlr 2