diff options
| author | Mahmoud <[email protected]> | 2017-10-11 20:05:51 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2017-10-11 20:58:12 -0400 |
| commit | 928351f92300b3517c96f5fabff02b245c87044a (patch) | |
| tree | 12b4e8e120ee24fe7cb0f55c159d7e38efabd34c /configs/GTX480 | |
| parent | 57b0578fcf9f38fdf6ef2828f2ff71e30c7d7098 (diff) | |
| parent | e643e2e56344db6264b17d7ffce28f22c8fbabe8 (diff) | |
Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
Diffstat (limited to 'configs/GTX480')
| -rw-r--r-- | configs/GTX480/gpgpusim.config | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 7d8d91e..03fcda1 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -30,7 +30,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -#For Fermi, DP unit =0, DP inst is executed on SFU unit instead +#For Fermi, DP unit =0, DP inst is executed on SFU -gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 -gpgpu_num_sp_units 2 -gpgpu_num_sfu_units 1 @@ -50,20 +50,20 @@ # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 -gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 --gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 # enable operand collector -gpgpu_operand_collector_num_units_sp 6 |