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authorTayler Hetherington <[email protected]>2012-09-19 14:51:45 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:20 -0700
commitb09eeed6aa36239f661d6452e996e3e5f8ef5984 (patch)
tree1d71f118193e7eb8b8de79d3f08a934067e5a143 /configs/GTX480
parentb19fd89f07b3221ea73f6c2442880c2e5c1e68a5 (diff)
Revision #2 of modifying the cache hierarchy.
Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations. Added WRITE_EVICT cache write policy. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
Diffstat (limited to 'configs/GTX480')
-rw-r--r--configs/GTX480/gpgpusim.config10
1 files changed, 5 insertions, 5 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index f481fc5..560f324 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -39,7 +39,7 @@
# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
--gpgpu_cache:dl1 32:128:4:L:B:m:A:P:N:32:8:8
+-gpgpu_cache:dl1 32:128:4:L:B:m:A:N:32:8:8
-gpgpu_shmem_size 49152
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
@@ -47,12 +47,12 @@
#-gpgpu_shmem_size 16384
# 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:256:8:L:B:m:A:S:W:32:4:4
+-gpgpu_cache:dl2 64:256:8:L:B:m:A:W:32:4:4
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 4:128:4:L:R:f:A:P:N:2:32:4
--gpgpu_tex_cache:l1 4:128:24:L:R:m:F:P:N:128:4:128:2
--gpgpu_const_cache:l1 64:64:2:L:R:f:A:P:N:2:32:4
+-gpgpu_cache:il1 4:128:4:L:R:f:A:N:2:32:4
+-gpgpu_tex_cache:l1 4:128:24:L:R:m:F:N:128:4:128:2
+-gpgpu_const_cache:l1 64:64:2:L:R:f:A:N:2:32:4
-gpgpu_num_reg_banks 16