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authortgrogers <[email protected]>2018-02-21 22:46:20 -0500
committertgrogers <[email protected]>2018-02-21 22:46:20 -0500
commit71d9ada37b64360a216dbceef5b7a26a6cab8480 (patch)
treeac0180ec5fb467ea54cea51f9105c4c76e3ac26e /configs/GeForceGTX750Ti
parent7796a731c2a7d14a58d1369af62c8ad589c63921 (diff)
parent4a94401a277342cfd0799863b1a07abc95f954c7 (diff)
merging in the mainline
Diffstat (limited to 'configs/GeForceGTX750Ti')
-rw-r--r--configs/GeForceGTX750Ti/gpgpusim.config17
1 files changed, 9 insertions, 8 deletions
diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
index 8b030b6..9366f93 100644
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/GeForceGTX750Ti/gpgpusim.config
@@ -28,10 +28,11 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
-gpgpu_num_sp_units 8
-gpgpu_num_sfu_units 32
+-gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -42,21 +43,21 @@
-ptx_opcode_latency_dp 8,19,8,8,330
-ptx_opcode_initiation_dp 8,16,8,8,130
--gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
-gmem_skip_L1D 1
-gpgpu_shmem_size 65536
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
--gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6