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authorAkshay Jain <[email protected]>2018-04-01 12:51:29 -0400
committerAkshay Jain <[email protected]>2018-04-01 12:51:29 -0400
commit12f2a2c791747dc38a53553026ed8122e8e08988 (patch)
tree14083fb3fe30b8801ff58de738b66cde9cee80f8 /configs/Pascal-P102-GDDR5X
parent0c6928caf8814bf9bd37602bffe6b7b0021f2585 (diff)
parentf373275550b689efaf9c60017ff11d4450d71091 (diff)
Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/jain156/gpgpu-sim_distribution into dev-purdue-integration
Diffstat (limited to 'configs/Pascal-P102-GDDR5X')
-rw-r--r--configs/Pascal-P102-GDDR5X/gpgpusim.config5
1 files changed, 5 insertions, 0 deletions
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config
index 0c6c126..3097d19 100644
--- a/configs/Pascal-P102-GDDR5X/gpgpusim.config
+++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config
@@ -6,6 +6,7 @@
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 61
+-gpgpu_ignore_resources_limitation 1
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
@@ -62,7 +63,11 @@
# Pascal GP102 has 24KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres is used
-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
-gmem_skip_L1D 1
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32