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| author | Mahmoud <[email protected]> | 2017-10-11 20:05:51 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2017-10-11 20:58:12 -0400 |
| commit | 928351f92300b3517c96f5fabff02b245c87044a (patch) | |
| tree | 12b4e8e120ee24fe7cb0f55c159d7e38efabd34c /configs/Pascal-P102-GDDR5X | |
| parent | 57b0578fcf9f38fdf6ef2828f2ff71e30c7d7098 (diff) | |
| parent | e643e2e56344db6264b17d7ffce28f22c8fbabe8 (diff) | |
Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
Diffstat (limited to 'configs/Pascal-P102-GDDR5X')
| -rw-r--r-- | configs/Pascal-P102-GDDR5X/gpgpusim.config | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 4400454..8b02680 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -33,9 +33,9 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6 +-gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 @@ -60,20 +60,20 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,S:128:8,8 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:4,4:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 # 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units @@ -83,8 +83,8 @@ -gpgpu_operand_collector_num_units_dp 6 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_sfu 4 +-gpgpu_operand_collector_num_out_ports_sfu 4 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 -gpgpu_operand_collector_num_in_ports_dp 1 |