diff options
| author | Mahmoud Abdallah <[email protected]> | 2017-11-19 00:29:29 -0500 |
|---|---|---|
| committer | Mahmoud Abdallah <[email protected]> | 2017-11-19 00:29:29 -0500 |
| commit | 8719ea402730f6f429e32d63304f9af79bb83df0 (patch) | |
| tree | 505a769470e93dd3fec4d0416ebfebefa4eb1bd5 /configs/PascalTitanX | |
| parent | 68cc9491f40e41d6421a2e6b068b4302cedf80ec (diff) | |
improving the accuracy of titanX
Diffstat (limited to 'configs/PascalTitanX')
| -rw-r--r-- | configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 4191eb0..4407870 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -21,7 +21,7 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -105,7 +105,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 100 -dram_latency 100 # dram model config @@ -130,8 +130,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" # Pascal GP102 has four schedulers per core -gpgpu_num_sched_per_core 4 |