diff options
| author | Timothy G Rogers <[email protected]> | 2018-02-21 15:39:03 -0500 |
|---|---|---|
| committer | GitHub Enterprise <[email protected]> | 2018-02-21 15:39:03 -0500 |
| commit | 4a94401a277342cfd0799863b1a07abc95f954c7 (patch) | |
| tree | 189adf02f534869654c7ebe5f5dd4c4838def3a3 /configs/QuadroFX5600 | |
| parent | 275e5813f4ef3ef92851d1a3752d1bffaabcdb50 (diff) | |
| parent | 6a2f9978b9325fb78e8af1be5d5aaf90814e08d7 (diff) | |
Merge pull request #6 from abdallm/dev-purdue-integration
HBM model + all Mahmoud's changes to the sim
Diffstat (limited to 'configs/QuadroFX5600')
| -rw-r--r-- | configs/QuadroFX5600/gpgpusim.config | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config index cb87b65..e3cab18 100644 --- a/configs/QuadroFX5600/gpgpusim.config +++ b/configs/QuadroFX5600/gpgpusim.config @@ -17,10 +17,11 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,1,1,1,1,1,1 +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 -gpgpu_num_sp_units 1 -gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" @@ -32,10 +33,10 @@ -ptx_opcode_initiation_dp 8,8,8,8,130 # memory stage behaviour --gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 -gpgpu_cache:dl2_texture_only 1 # TLB parameters |