-Change Fermi configuration folder name to GTX480

-Adding TeslaC2050 configuration: this configuration was initially integrated in the power branch from fermi-boktor branch to get IPC correlation with the Tesla card on Inder pc (pc-12). The IPC correlation data on the public wiki uses this configuration. The latest update for dram GDDR5 configuration Wilson added is also integrated.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13225]

2 files changed, 163 insertions, 0 deletions

diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
new file mode 100644
index 0000000..0d9fb61
--- /dev/null
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -0,0 +1,114 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 12 
+
+# high level architecture configuration
+-gpgpu_n_clusters 14
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 575.0:1150.0:575.0:1500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1024:32
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq>
+-gpgpu_cache:dl1  32:128:4:L:R:m,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1  64:128:6:L:R:f,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 256 bytes 8-way for each memory partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:256:8:L:R:m,A:32:4,4
+-gpgpu_cache:dl2_texture_only 0 
+
+-gpgpu_cache:il1 4:128:4:L:R:f,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24:L:R:m,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4
+
+-gpgpu_num_reg_banks 16
+
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_islip.txt 
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_dram_sched_queue_size 16
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBBCCCC.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
+# -gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:CL=12:
+#                        WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2
+-gpgpu_dram_timing_opt 16:2:6:12:28:12:40:12:4:5:12:4:3:2
+
+# GDDR3
+#-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+# Using cuobjdump to extract ptx/SASS
+-gpgpu_ptx_use_cuobjdump 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 1
+-gpgpu_ptx_save_converted_ptxplus 1
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-visualizer_enabled 0
+-keep 1
diff --git a/configs/TeslaC2050/icnt_config_islip.txt b/configs/TeslaC2050/icnt_config_islip.txt
new file mode 100644
index 0000000..f2bb38e
--- /dev/null
+++ b/configs/TeslaC2050/icnt_config_islip.txt
@@ -0,0 +1,49 @@
+use_map = 0;
+flit_size = 32; 
+
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 23;
+n = 1;
+
+// Routing
+routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+// Flow control
+num_vcs     = 1; //4; 
+vc_buf_size = 8; //16;
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip;//i1_pim; //islip; //pim
+sw_allocator = islip;//i1_pim;//islip; //pim
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 0;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic (DO NOT CHANGE THIS)
+traffic = gpgpusim; 
+
+//not used in gpgpusim
+// const_flits_per_packet = 3;
+injection_process = gpgpu_injector;
+// Simulation 
+//not used in gpgpusim
+sim_type       = latency;
+injection_rate = 0.1;
+
+
+// Statistics for Interconnection (Added for GPGPU-Sim)
+MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
+DISPLAY_LAT_DIST = 1; // distribution of packet latencies
+DISPLAY_HOP_DIST = 1; // distribution of hop counts
+DISPLAY_PAIR_LATENCY = 0;