Merge pull request #79 from purdue-aalp/dev

Merging dev-purdue to public-dev-gpgpu-sim-repo

1 files changed, 99 insertions, 0 deletions

diff --git a/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
new file mode 100644
index 0000000..6f836ee
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
@@ -0,0 +1,99 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 12
+
+# high level architecture configuration
+-gpgpu_n_clusters 8 
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 6 
+-gpgpu_clock_domains 337.5:600.0:600.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 12
+
+-gpgpu_occupancy_sm_number 12
+#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
+-gpgpu_shader_core_pipeline 768:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+# TLB parameters
+#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8
+#-gpgpu_tlbl2_latency 45
+
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_islip.icnt 
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 55
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+
+
+# Using cuobjdump to extract ptx/SASS
+-gpgpu_ptx_use_cuobjdump 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+-power_trace_enabled 0
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_quadrofx5600.xml 
+
+-steady_power_levels_enabled 1
+-steady_state_definition 8,4