merged with memory subsytem. Regression is passing but tensorcore kernel is stuck in deadlock

2 files changed, 157 insertions, 0 deletions

diff --git a/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
new file mode 100644
index 0000000..cfe9cac
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
@@ -0,0 +1,69 @@
+//18*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we donot use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 18;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
new file mode 100644
index 0000000..fef1110
--- /dev/null
+++ b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
@@ -0,0 +1,88 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 13
+
+# high level architecture configuration
+-gpgpu_n_clusters 10 
+-gpgpu_n_cores_per_cluster 3
+-gpgpu_n_mem 8 
+-gpgpu_clock_domains 325.0:650.0:650.0:800.0 
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 13
+
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
+-gpgpu_num_sp_units 1
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 1,1,19,25,145
+-ptx_opcode_initiation_int 1,1,4,4,32
+-ptx_opcode_latency_fp 1,1,1,1,30
+-ptx_opcode_initiation_fp 1,1,1,1,5
+-ptx_opcode_latency_dp 8,8,8,8,335
+-ptx_opcode_initiation_dp 8,8,8,8,130
+
+# memory stage behaviour
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:dl2_texture_only 1
+
+-gpgpu_shmem_warp_parts 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_quadro_islip.icnt
+
+# dram scheduler config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 325MHz = 74
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 58
+
+# dram model config
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-dram_data_command_freq_ratio 2  # GDDR3 is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# enable operand collector 
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+
+-visualizer_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0