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authorMahmoud <[email protected]>2018-11-07 20:30:02 -0500
committerMahmoud <[email protected]>2018-11-07 20:30:02 -0500
commit111cca2a061fe4f247be930cb44fdcdaec2b59f5 (patch)
tree34f85262fabff8ccb8590a9c9eb57c1e88b5d4e8 /configs/tested-cfgs/SM2_GTX480/gpgpusim.config
parent7d42f5849aa1abb4f081803843ea78009d5b20ce (diff)
Adding INT unit, fixing tensor core latency, updating config files
Diffstat (limited to 'configs/tested-cfgs/SM2_GTX480/gpgpusim.config')
-rw-r--r--configs/tested-cfgs/SM2_GTX480/gpgpusim.config7
1 files changed, 4 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 4096b09..d71b2fd 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -30,9 +30,10 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-#For Fermi, DP unit =0, DP inst is executed on SFU
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+# For Fermi, DP unit =0, DP inst is executed on SFU
+# For Fermi, INT unit =0, INT inst is executed on SP
+-gpgpu_pipeline_widths 2,0,0,1,1,2,0,0,1,1,2
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 1
-gpgpu_num_dp_units 0