diff options
| author | boyealKim <[email protected]> | 2019-07-21 02:28:59 +0900 |
|---|---|---|
| committer | boyealKim <[email protected]> | 2019-07-21 02:28:59 +0900 |
| commit | d212d7e5fdcc9f8e10779d5cfb398a451f8ad033 (patch) | |
| tree | d3c179be2725d22f7fece9f6bb6e878e7c29b0ff /configs/tested-cfgs/SM6_TITANX/gpgpusim.config | |
| parent | a1e2c4273542ca78098c9f4f25eebc087e0aec37 (diff) | |
take account of shfl latency
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 2fe898a..da1af48 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -56,11 +56,11 @@ # Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" +# "ADD,MAX,MUL,MAD,DIV,SHFL" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 |