diff options
| author | tgrogers <[email protected]> | 2019-05-19 09:35:48 -0400 |
|---|---|---|
| committer | tgrogers <[email protected]> | 2019-05-19 09:35:48 -0400 |
| commit | 206ccbe8c0f712c802f8919497ca70bff1aa6a1e (patch) | |
| tree | 82ef1ef2631a0c8c32c2ce44319e96b944c52730 /configs/tested-cfgs/SM6_TITANX | |
| parent | 8c45f47e1b683d9904956659340a394321c6682d (diff) | |
| parent | 8fb484e4120a08e896f53424e9f4f46710966970 (diff) | |
Merge branch 'dev' of github.com:purdue-aalp/gpgpu-sim_distribution into dev
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt (renamed from configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt) | 0 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 12 |
2 files changed, 11 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt index dec4789..dec4789 100644 --- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt +++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index cb23ab3..2fe898a 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -8,6 +8,16 @@ -gpgpu_ptx_force_max_capability 61 -gpgpu_ignore_resources_limitation 1 +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + +# Compute Capability +-gpgpu_compute_capability_major 6 +-gpgpu_compute_capability_minor 1 + # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 @@ -92,7 +102,7 @@ # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 |