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authorPSuchita <[email protected]>2019-05-30 00:36:43 -0700
committerGitHub <[email protected]>2019-05-30 00:36:43 -0700
commit580a244665a4cf6855320dc209a66dc2fe81c645 (patch)
tree086c2973182f844dd090e60b5010f8b5aa6df06b /configs/tested-cfgs/SM6_TITANX
parent51c853e42c805275c64ee90c1c025e4b111fc570 (diff)
parent5837143ef70e20c362083b36c55e4c473f59f358 (diff)
Merge pull request #4 from gpgpu-sim/dev
Dev
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
-rw-r--r--configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt (renamed from configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt)0
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config2
2 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
index dec4789..dec4789 100644
--- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 23d044c..2fe898a 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -102,7 +102,7 @@
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 12 KB Const
-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4