Merge pull request #83 from purdue-aalp/dev

INT unit, sub-core-model, Increase L1 throughput and add tensor core config parameters

1 files changed, 7 insertions, 11 deletions

diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 3842508..cb23ab3 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -35,10 +35,11 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
 -gpgpu_num_sp_units 2
 -gpgpu_num_sfu_units 2
 -gpgpu_num_dp_units 1
@@ -86,6 +87,7 @@
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 1
+-memory_partition_indexing 0
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -131,13 +133,8 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
+-gpgpu_dram_return_queue_size 64
 
 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
 # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
@@ -149,7 +146,7 @@
 -gpgpu_mem_address_mask 1
 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
 
-# Use the same GDDR5 timing
+# Use the same GDDR5 timing, scaled to 2500MHZ
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
                         CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
 
@@ -176,7 +173,6 @@
 
 # power model configs, disable it untill we create a real energy model for Pascal 102
 -power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality
 #-trace_enabled 1