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| author | Tor Aamodt <[email protected]> | 2020-05-21 08:57:11 -0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-05-21 08:57:11 -0700 |
| commit | 76217d80d9aa33126b4254f5e899f882bbc6f2fd (patch) | |
| tree | 4f461a6f417f76956748fafcfb89b664f54bf6a9 /configs/tested-cfgs/SM6_TITANX | |
| parent | e7fbfaa347c0acf8a6702c1e684a8e2ad8d3f733 (diff) | |
| parent | e9e9fcf5957530ecb927aecb5ea238e4b78a4f45 (diff) | |
Merge pull request #178 from purdue-aalp/dev
Merging with the last few months of work at Purdue
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index ba37c0c..391269e 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -81,6 +81,7 @@ -gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 49152 +-gpgpu_shmem_sizeDefault 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 # By default, L1 cache is disabled in Pascal P102. |