aboutsummaryrefslogtreecommitdiff
path: root/configs/tested-cfgs/SM6_TITANX
diff options
context:
space:
mode:
authorMengchi Zhang <[email protected]>2019-09-06 20:57:26 -0400
committerGitHub <[email protected]>2019-09-06 20:57:26 -0400
commitbffc964722e4e6275c6cf78484791528986ceecd (patch)
tree609220dbb901dc83ab5172205c06580fb035d56b /configs/tested-cfgs/SM6_TITANX
parent07f7494e588301d898122837cb73b34380a2e041 (diff)
parentbeeea4ae9ca4da8362e2020b965d78e359b68ceb (diff)
Merge pull request #4 from purdue-aalp/dev
Merge aalp dev into Mengchi
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config1
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 2fe898a..e6d8f1d 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -81,6 +81,7 @@
-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_shmem_size 49152
+-gpgpu_shmem_sizeDefault 49152
-gpgpu_shmem_size_PrefL1 49152
-gpgpu_shmem_size_PrefShared 49152
# By default, L1 cache is disabled in Pascal P102.