diff options
| author | Tim Rogers <[email protected]> | 2019-05-13 19:42:43 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-05-13 19:42:43 -0400 |
| commit | cbb929b6f15f63f0b104e2acac7a17f02c0208fe (patch) | |
| tree | ed2bf825d27848c818a9293075cf9b9d73a26864 /configs/tested-cfgs/SM6_TITANX | |
| parent | f507979bcf0f14d1e5843c9b08613d6b0a4bb7a2 (diff) | |
| parent | 059dabc1af44b8eb60f0cacc8d5c2d06f1e85a00 (diff) | |
Merge pull request #118 from mkhairy/dev
Integrating Mahmoud's changes that improve simulation speed by 2-3x.
Also includes a change that mitigates memory channel conflicts by using a random hashing function.
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt (renamed from configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt) | 0 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 2 |
2 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt index dec4789..dec4789 100644 --- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt +++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 23d044c..2fe898a 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -102,7 +102,7 @@ # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex -# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 |