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authorMahmoud <[email protected]>2019-04-25 16:01:03 -0400
committerMahmoud <[email protected]>2019-04-25 16:01:03 -0400
commitd7fd62c23db88a71e1fb327b584504a5270d01e0 (patch)
treebb43692d90ec94b98d08f7fdb1751e3ca7e4c8ea /configs/tested-cfgs/SM6_TITANX
parent0cf1f587d5bcc449c679371ac966f26db706deca (diff)
adding v100 config file
Diffstat (limited to 'configs/tested-cfgs/SM6_TITANX')
-rw-r--r--configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt (renamed from configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt)0
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config2
2 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
index dec4789..dec4789 100644
--- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index cb23ab3..73e3951 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -92,7 +92,7 @@
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
# 48 KB Tex
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 12 KB Const
-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4