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authorMahmoud Khairy A. Abdallah <[email protected]>2020-05-18 21:49:34 -0400
committerMahmoud Khairy A. Abdallah <[email protected]>2020-05-18 21:49:34 -0400
commit52204ff08a9c9a21a99fee3f976d2a419c014fec (patch)
tree3b6e888267ac1aae2af024cf7ef80d5f921600e4 /configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
parentfe8dd7eadbb67b9e917c92c9c540812db35fce37 (diff)
fixing some failing apps
Diffstat (limited to 'configs/tested-cfgs/SM75_RTX2060/gpgpusim.config')
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/gpgpusim.config6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index e8329dd..b89971e 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -33,9 +33,9 @@
# volta clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
--gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0
+-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0
# boost mode
-# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0
+# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0
# shader core pipeline config
-gpgpu_shader_registers 65536
@@ -156,7 +156,7 @@
-gpgpu_n_mem_per_ctrlr 1
-gpgpu_dram_buswidth 2
-gpgpu_dram_burst_length 16
--dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing
+-dram_data_command_freq_ratio 4
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS