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authorMahmoud <[email protected]>2019-10-04 21:32:38 -0400
committerMahmoud <[email protected]>2019-10-04 21:32:38 -0400
commit326a038bc3b7386ccd2f16ebee6e3cc44eb677e5 (patch)
tree3bb401bc5bd5e37738a9b6f6db4bd539f58ae207 /configs/tested-cfgs/SM7_QV100/gpgpusim.config
parentcaea1a724ebd32a9c11e2af25e79862f84baf9d6 (diff)
increase RF banks
Diffstat (limited to 'configs/tested-cfgs/SM7_QV100/gpgpusim.config')
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config8
1 files changed, 5 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index c0d22ee..23a57fa 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -122,11 +122,13 @@
-sub_core_model 1
# disable specialized operand collectors and use generic operand collectors instead
-enable_specialized_operand_collector 0
--gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_units_gen 32
-gpgpu_operand_collector_num_in_ports_gen 8
-gpgpu_operand_collector_num_out_ports_gen 8
-# volta has 8 banks, 4 schedulers, two banks per scheduler
--gpgpu_num_reg_banks 8
+# Volta has 8 banks, 4 schedulers, two banks per scheduler
+# However, since we do not model register file cache (RFC), we increase the number of banks to 32 to
+# resuce banks conflits, mitigate RFC impact, and matche the hardware performance. To Do: RFC
+-gpgpu_num_reg_banks 32
# shared memory bankconflict detection
-gpgpu_shmem_num_banks 32